component
VIPER0PHDTR
Public Made by Adomby adom
STMicroelectronics AC-DC Controllers And Regulators, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# VIPER0PHDTR++**STMicroelectronics** · AC-DC Controllers And Regulators · SO-16++VIPER0PHDTR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PGND | power_in | Power ground and MOSFET source; pulsed current from Power MOSFET must return through this pin and be connected to same ground plane as SGND with shortest trace. |+| 2 | EAGND | power_in | Error amplifier ground reference; connect directly to negative rail for non-isolated negative output converters, or short to SGND for positive output converters. |+| 3 | VCC | power_in | Controller supply voltage; internal high-voltage current source provides VCC capacitor charging current at startup and during steady-state operation; requires external storage capacitor across VCC-SGND and 0.1 μF bypass capacitor placed close to IC. |+| 4 | SGND | power_in | Signal ground; all groundings of bias components must connect to this pin and be kept separate from pulsed current return path. |+| 5 | FB | input | Direct feedback to inverting input of internal transconductance error amplifier, internally referenced to 1.2 V with respect to EAGND; accepts output voltage information via voltage divider. |+| 6 | COMP | output | Compensation output of internal error amplifier; compensation network placed between this pin and SGND to achieve control loop stability and good dynamic performance. |+| 7 | ON | input | ZPM exit control; IC is reactivated by forcing this pin to SGND for debounce time tDEB_ON; internal pull-up resistor keeps pin at VON level during normal operation. |+| 8 | OFF | input | ZPM enter control; IC enters ZPM by forcing this pin to SGND for debounce time tDEB_OFF; internal pull-up resistor keeps pin at VOFF level during normal operation. |+| 9 | N.C. | unconnected | Not internally connected; must be left floating to maintain safe clearance distance. |+| 10 | N.C. | unconnected | Not internally connected; must be left floating to maintain safe clearance distance. |+| 11 | N.C. | unconnected | Not internally connected; must be left floating to maintain safe clearance distance. |+| 12 | N.C. | unconnected | Not internally connected; must be left floating to maintain safe clearance distance. |+| 13 | DRAIN | output | MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation. |+| 14 | DRAIN | output | MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation. |+| 15 | DRAIN | output | MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation. |+| 16 | DRAIN | output | MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | SO-16 |+| Category | Power Management (PMIC) |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `VIPER0PHDTR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SO-16 (KiCad packages3D, STEP)+- 3D model files: `viper0phdtr-etched.step` / `viper0phdtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `viper0phdtr.step` / `viper0phdtr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8600478613796245504) (36 pp, sha256 `ada84337e66288b0`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/viper0phdtr-datasheet.pdf)
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pulsed current from Power MOSFET must return through this pin and be connected to same ground plane as SGND with shortest trace."+ },+ {+ "number": "2",+ "name": "EAGND",+ "type": "power_in",+ "description": "Error amplifier ground reference; connect directly to negative rail for non-isolated negative output converters, or short to SGND for positive output converters."+ },+ {+ "number": "3",+ "name": "VCC",+ "type": "power_in",+ "description": "Controller supply voltage; internal high-voltage current source provides VCC capacitor charging current at startup and during steady-state operation; requires external storage capacitor across VCC-SGND and 0.1 μF bypass capacitor placed close to IC."+ },+ {+ "number": "4",+ "name": "SGND",+ "type": "power_in",+ "description": "Signal ground; all groundings of bias components must connect to this pin and be kept separate from pulsed current return path."+ },+ {+ "number": "5",+ "name": "FB",+ "type": "input",+ "description": "Direct feedback to inverting input of internal transconductance error amplifier, internally referenced to 1.2 V with respect to EAGND; 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must be left floating to maintain safe clearance distance."+ },+ {+ "number": "11",+ "name": "N.C.",+ "type": "unconnected",+ "description": "Not internally connected; must be left floating to maintain safe clearance distance."+ },+ {+ "number": "12",+ "name": "N.C.",+ "type": "unconnected",+ "description": "Not internally connected; must be left floating to maintain safe clearance distance."+ },+ {+ "number": "13",+ "name": "DRAIN",+ "type": "output",+ "description": "MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation."+ },+ {+ "number": "14",+ "name": "DRAIN",+ "type": "output",+ "description": "MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation."+ },+ {+ "number": "15",+ "name": "DRAIN",+ "type": "output",+ "description": "MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation."+ },+ {+ "number": "16",+ "name": "DRAIN",+ "type": "output",+ "description": "MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "4/16 pins cited to the wrong page (name found elsewhere): ['11:N.C.@p3', '12:N.C.@p3', '14:DRAIN@p3', '15:DRAIN@p3']"+ ],+ "pages_sent": 11,+ "cost_usd": 0.0731,+ "at": "2026-10-07T02:45:42"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8600478613796245504",+ "pages": 36,+ "sha256": "ada84337e66288b0",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "viper0phdtr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "viper0phdtr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f6478a217cae3df29cbc70c44109eac63d1e136bf26a73b34b79a6439977388d",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}