component
USB6B1RL
Public Made by Adomby adom
STMicroelectronics ESD And Surge Protection (TVS/ESD), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUSB6B1RL
STMicroelectronics · ESD And Surge Protection (TVS/ESD) · SOIC-8
USB6B1RL from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Vcc | power_in | Supply rail pin, clamped by the integrated Transil diode (VBR = 6 V min at IR = 1 mA) and connected to the same node as pin 8; keep the track to the supply short, with 100 nF to ground recommended. |
| 2 | I/O1 | passive | Protected data line 1 input, connected internally to I/O1 on pin 7, with rail-to-rail clamping diodes to Vcc and GND (25 A peak pulse, 8/20 µs). |
| 3 | I/O2 | passive | Protected data line 2 input, connected internally to I/O2 on pin 6, with rail-to-rail clamping diodes to Vcc and GND (25 A peak pulse, 8/20 µs). |
| 4 | GND | power_in | Ground reference pin, connected to the same node as pin 5; keep the track to the ground plane short. |
| 5 | GND | power_in | Ground reference pin, connected to the same node as pin 4 (separate input and output pins, 4-point structure). |
| 6 | I/O2 | passive | Protected data line 2 output side, connected internally to I/O2 on pin 3 (4-point structure); capacitance between D+ and D- is 15 pF max. |
| 7 | I/O1 | passive | Protected data line 1 output side, connected internally to I/O1 on pin 2 (4-point structure); capacitance between D+ and D- is 15 pF max. |
| 8 | Vcc | power_in | Supply rail pin, connected to the same node as pin 1 (separate input and output pins, 4-point structure); leakage 10 µA max at VRM = 5.25 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Circuit Protection |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
USB6B1RL - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
usb6b1rl-etched.step/usb6b1rl-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);usb6b1rl.step/usb6b1rl.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (9 pp, sha256
2c5a8ac2e60be887, retrieved 2026-10-03, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).