component
USB3300-EZK
Public Made by Adomby adom
Microchip Tech USB Converters, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "usb3300-ezk",
"version": "0.1.0",
"type": "component",
"description": "Microchip Tech USB Converters, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"interface",
"usb3300-ezk",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"usb3300-ezk.kicad_sym",
"usb3300-ezk.kicad_mod",
"usb3300-ezk.glb",
"usb3300-ezk.step",
"usb3300-ezk.lbr",
"docs/hero.png",
"docs/usb3300-ezk-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"usb3300-ezk-hero.glb",
"usb3300-ezk-hero.overlay.json",
"usb3300-ezk-etched.glb"
],
"component": {
"mpn": "USB3300-EZK",
"manufacturer": "Microchip Tech",
"package": "QFN-32-EP(5x5)",
"pin_count": 33,
"category": "Interface",
"subcategory": "USB Converters",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586182626059431936",
"parts": {
"symbol": "usb3300-ezk.kicad_sym",
"footprint": "usb3300-ezk.kicad_mod",
"model_3d": "usb3300-ezk-hero.glb",
"model_3d_plain": "usb3300-ezk-etched.glb",
"model_3d_step": "usb3300-ezk-etched.step",
"model_3d_step_plain": "usb3300-ezk.step",
"lbr": "usb3300-ezk.lbr"
},
"distributor_links": {
"lcsc": "C108954",
"digikey": "638-1034-ND",
"mouser": "886-USB3300-EZK"
},
"distributor_check": {
"checked_at": "2026-10-18T01:15:03Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "638-1034-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "886-USB3300-EZK",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "GND",
"type": "power_in",
"description": "Ground pin of the device."
},
{
"number": "2",
"name": "GND",
"type": "power_in",
"description": "Ground pin of the device."
},
{
"number": "3",
"name": "CPEN",
"type": "output",
"description": "External 5 volt supply enable used to enable the external Vbus power supply; the pin is low on POR."
},
{
"number": "4",
"name": "VBUS",
"type": "power_in",
"description": "VBUS pin of the USB cable, used for the Vbus comparator inputs and for Vbus pulsing during session request protocol."
},
{
"number": "5",
"name": "ID",
"type": "input",
"description": "ID pin of the USB cable; it can be floated for non-OTG applications, reading 0 for an A-Device and 1 for a B-Device."
},
{
"number": "6",
"name": "VDD3.3",
"type": "power_in",
"description": "3.3V supply, with a 0.1uF bypass capacitor to the PCB ground plane."
},
{
"number": "7",
"name": "DP",
"type": "bidirectional",
"description": "D+ pin of the USB cable."
},
{
"number": "8",
"name": "DM",
"type": "bidirectional",
"description": "D- pin of the USB cable."
},
{
"number": "9",
"name": "RESET",
"type": "input",
"description": "Optional active high transceiver reset equivalent to a write to ULPI Reset bit 5 of address 04h; it has an integrated pull-down and may be floated or tied to ground if unused."
},
{
"number": "10",
"name": "EXTVBUS",
"type": "input",
"description": "External Vbus detect input to connect to the fault output of an external USB power switch or Vbus Valid comparator, with a pull-down to prevent floating when UseExternalVbusIndicator is 0."
},
{
"number": "11",
"name": "NXT",
"type": "output",
"description": "The PHY asserts NXT to throttle data, indicating when the current byte has been accepted by the PHY."
},
{
"number": "12",
"name": "DIR",
"type": "output",
"description": "Controls data bus direction: the PHY drives DIR high when it has data for the Link and pulls it high when it cannot accept data, such as during PLL start-up."
},
{
"number": "13",
"name": "STP",
"type": "input",
"description": "The Link asserts STP for one clock cycle to stop the data stream on the bus; the pin includes the interface protection pull-up described in section 6.1.9.3."
},
{
"number": "14",
"name": "CLKOUT",
"type": "output",
"description": "60MHz reference clock output to which all ULPI signals are synchronized on the rising edge."
},
{
"number": "15",
"name": "VDD1.8",
"type": "power_out",
"description": "1.8V digital supply from the on-chip regulator when REG_EN is active; a 0.1uF capacitor to ground is required and this pin must be connected to pin 26."
},
{
"number": "16",
"name": "VDD3.3",
"type": "power_in",
"description": "3.3V supply, with a 0.1uF bypass capacitor to the PCB ground plane."
},
{
"number": "17",
"name": "DATA[7]",
"type": "bidirectional",
"description": "MSB of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR."
},
{
"number": "18",
"name": "DATA[6]",
"type": "bidirectional",
"description": "Bit 6 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR."
},
{
"number": "19",
"name": "DATA[5]",
"type": "bidirectional",
"description": "Bit 5 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR."
},
{
"number": "20",
"name": "DATA[4]",
"type": "bidirectional",
"description": "Bit 4 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR."
},
{
"number": "21",
"name": "DATA[3]",
"type": "bidirectional",
"description": "Bit 3 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR."
},
{
"number": "22",
"name": "DATA[2]",
"type": "bidirectional",
"description": "Bit 2 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR."
},
{
"number": "23",
"name": "DATA[1]",
"type": "bidirectional",
"description": "Bit 1 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR."
},
{
"number": "24",
"name": "DATA[0]",
"type": "bidirectional",
"description": "LSB of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR."
},
{
"number": "25",
"name": "VDD3.3",
"type": "power_in",
"description": "3.3V supply, with a 0.1uF bypass capacitor to the PCB ground plane."
},
{
"number": "26",
"name": "VDD1.8",
"type": "power_out",
"description": "1.8V digital supply from the on-chip regulator when REG_EN is active; requires a 4.7uF low-ESR capacitor to ground when internal regulators are used and must be connected to pin 15, not to VDDA1.8."
},
{
"number": "27",
"name": "XO",
"type": "output",
"description": "Crystal pin for the 24MHz crystal connected across XI and XO; it should be left floating when an external clock drives XI."
},
{
"number": "28",
"name": "XI",
"type": "input",
"description": "Crystal pin supporting a 24MHz crystal, or an external 24MHz clock source driven into XI in place of a crystal."
},
{
"number": "29",
"name": "VDDA1.8",
"type": "power_out",
"description": "1.8V analog supply from the on-chip regulator when REG_EN is active; requires 0.1uF plus 4.7uF capacitors to ground when internal regulators are used."
},
{
"number": "30",
"name": "VDD3.3",
"type": "power_in",
"description": "Analog 3.3V supply; a 0.1uF low-ESR bypass capacitor to the PCB ground plane is recommended."
},
{
"number": "31",
"name": "REG_EN",
"type": "bidirectional",
"description": "On-chip 1.8V regulator enable; connecting it to ground disables both internal regulators, requiring an external 1.8V supply on VDDA1.8 and VDD1.8 after VDD3.3 reaches at least 2.64V."
},
{
"number": "32",
"name": "RBIAS",
"type": "passive",
"description": "External 12KΩ ±1% bias resistor connected to ground."
},
{
"number": "33",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet's pin table lists a 'GND FLAG' exposed pad (ground flag) that is not a numbered pin (1; Pins 15, 26 and 29 (VDD1.8, VDD1.8, VDDA1.8) are typed power_out because they are on-chip regulator ; The datasheet gives no direction for RBIAS (pin 32), only 'Analog, CMOS'. It is typed passive becaus",
"exposed pad 33 added from the footprint",
"1/33 pin names appear NOWHERE in the datasheet text: ['27:XO@p9']"
],
"pages_sent": 17,
"cost_usd": 0.1051,
"at": "2026-10-18T01:14:00"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586182626059431936",
"pages": 53,
"sha256": "33e73e37f5110cb9",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 33,
"described": 33,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "usb3300-ezk.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5.0,
5.0,
0.875
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",
"checked": "2026-10-18",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "usb3300-ezk-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5.0,
5.0,
0.875
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "3d2ab51c20c9b5beb22e67d0dc8e211055f0afd183dc6a701751c9bb43cded62",
"checked": "2026-10-18",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}