component
USB3300-EZK
Public Made by Adomby adom
Microchip Tech USB Converters, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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|---|---|
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| README.md | 17d ago |
| usb3300-ezk-etched.glb | 17d ago |
| usb3300-ezk-etched.step | 17d ago |
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| usb3300-ezk-hero.overlay.json | 17d ago |
| usb3300-ezk.glb | 17d ago |
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USB3300-EZK
Microchip Tech · USB Converters · QFN-32-EP(5x5)
USB3300-EZK from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin of the device. |
| 2 | GND | power_in | Ground pin of the device. |
| 3 | CPEN | output | External 5 volt supply enable used to enable the external Vbus power supply; the pin is low on POR. |
| 4 | VBUS | power_in | VBUS pin of the USB cable, used for the Vbus comparator inputs and for Vbus pulsing during session request protocol. |
| 5 | ID | input | ID pin of the USB cable; it can be floated for non-OTG applications, reading 0 for an A-Device and 1 for a B-Device. |
| 6 | VDD3.3 | power_in | 3.3V supply, with a 0.1uF bypass capacitor to the PCB ground plane. |
| 7 | DP | bidirectional | D+ pin of the USB cable. |
| 8 | DM | bidirectional | D- pin of the USB cable. |
| 9 | RESET | input | Optional active high transceiver reset equivalent to a write to ULPI Reset bit 5 of address 04h; it has an integrated pull-down and may be floated or tied to ground if unused. |
| 10 | EXTVBUS | input | External Vbus detect input to connect to the fault output of an external USB power switch or Vbus Valid comparator, with a pull-down to prevent floating when UseExternalVbusIndicator is 0. |
| 11 | NXT | output | The PHY asserts NXT to throttle data, indicating when the current byte has been accepted by the PHY. |
| 12 | DIR | output | Controls data bus direction: the PHY drives DIR high when it has data for the Link and pulls it high when it cannot accept data, such as during PLL start-up. |
| 13 | STP | input | The Link asserts STP for one clock cycle to stop the data stream on the bus; the pin includes the interface protection pull-up described in section 6.1.9.3. |
| 14 | CLKOUT | output | 60MHz reference clock output to which all ULPI signals are synchronized on the rising edge. |
| 15 | VDD1.8 | power_out | 1.8V digital supply from the on-chip regulator when REG_EN is active; a 0.1uF capacitor to ground is required and this pin must be connected to pin 26. |
| 16 | VDD3.3 | power_in | 3.3V supply, with a 0.1uF bypass capacitor to the PCB ground plane. |
| 17 | DATA[7] | bidirectional | MSB of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR. |
| 18 | DATA[6] | bidirectional | Bit 6 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR. |
| 19 | DATA[5] | bidirectional | Bit 5 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR. |
| 20 | DATA[4] | bidirectional | Bit 4 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR. |
| 21 | DATA[3] | bidirectional | Bit 3 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR. |
| 22 | DATA[2] | bidirectional | Bit 2 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR. |
| 23 | DATA[1] | bidirectional | Bit 1 of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR. |
| 24 | DATA[0] | bidirectional | LSB of the 8-bit ULPI bidirectional data bus with a pull-low; bus ownership is determined by DIR. |
| 25 | VDD3.3 | power_in | 3.3V supply, with a 0.1uF bypass capacitor to the PCB ground plane. |
| 26 | VDD1.8 | power_out | 1.8V digital supply from the on-chip regulator when REG_EN is active; requires a 4.7uF low-ESR capacitor to ground when internal regulators are used and must be connected to pin 15, not to VDDA1.8. |
| 27 | XO | output | Crystal pin for the 24MHz crystal connected across XI and XO; it should be left floating when an external clock drives XI. |
| 28 | XI | input | Crystal pin supporting a 24MHz crystal, or an external 24MHz clock source driven into XI in place of a crystal. |
| 29 | VDDA1.8 | power_out | 1.8V analog supply from the on-chip regulator when REG_EN is active; requires 0.1uF plus 4.7uF capacitors to ground when internal regulators are used. |
| 30 | VDD3.3 | power_in | Analog 3.3V supply; a 0.1uF low-ESR bypass capacitor to the PCB ground plane is recommended. |
| 31 | REG_EN | bidirectional | On-chip 1.8V regulator enable; connecting it to ground disables both internal regulators, requiring an external 1.8V supply on VDDA1.8 and VDD1.8 after VDD3.3 reaches at least 2.64V. |
| 32 | RBIAS | passive | External 12KΩ ±1% bias resistor connected to ground. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-32-EP(5x5) |
| Category | Interface |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum VBUS, ID, EXTVBUS, DP, and DM voltage to GND | VMAX_5V | -0.5 | 5.5 | V | 11 | ||
| Maximum VDD1.8 and VDDA1.8 voltage to Ground | VMAX_1.8V | -0.5 | 2.5 | V | 11 | ||
| Maximum 3.3V supply voltage to Ground | VMAX_3.3V | -0.5 | 4 | V | 11 | ||
| Maximum I/O voltage to Ground | VMAX_IN | -0.5 | 4 | V | 11 | ||
| Operating Temperature | TMAX_OP | -40 | 85 | C | 11 | ||
| Storage Temperature | TMAX_STG | -55 | 150 | C | 11 | ||
| VDD3.3 to GND | VDD3.3 | 3 | 3.3 | 3.6 | V | 11 | |
| Input Voltage on Digital Pins | VI | 0 | V | 11 | |||
| Voltage on Analog I/O Pins (DP, DM, ID) | VI(I/O) | 0 | V | 11 | |||
| VBUS to GND | VVBUS | 0 | 5.25 | 11 | |||
| Ambient Temperature | TA | -40 | 85 | C | 11 | ||
| FS Idle 3.3V Current | IAVG(FS33) | 18.8 | 21.9 | mA | FS idle not data transfer | 12 | |
| FS Idle 1.8V Current | IAVG(FS18) | 36.4 | 43.2 | mA | FS idle not data transfer | 12 | |
| FS Transmit 3.3V Current | IAVG(FSTX33) | 36 | 41.6 | mA | FS current during data transmit | 12 | |
| FS Transmit 1.8V Current | IAVG(FSTX18) | 36.8 | 43.2 | mA | FS current during data transmit | 12 | |
| FS Receive 3.3V Current | IAVG(FSRX33) | 22.5 | 27 | mA | FS current during data receive | 12 | |
| FS Receive 1.8V Current | IAVG(FSRX18) | 36.7 | 43.4 | mA | FS current during data receive | 12 | |
| HS Idle 3.3V Current | IAVG(HS33) | 22.1 | 25.4 | mA | HS idle not data transfer | 12 | |
| HS Idle 1.8V Current | IAVG(HS18) | 38.7 | 45.6 | mA | HS idle not data transfer | 12 | |
| HS Transmit 3.3V Current | IAVG(HSTX33) | 25.4 | 29 | mA | HS current during data transmit | 12 | |
| HS Transmit 1.8V Current | IAVG(HSTX18) | 39.1 | 46.2 | mA | HS current during data transmit | 12 | |
| HS Receive 3.3V Current | IAVG(HSRX33) | 23 | 26.6 | mA | HS current during data receive | 12 | |
| HS Receive 1.8V Current | IAVG(HSRX18) | 39.6 | 46.8 | mA | HS current during data receive | 12 | |
| Suspend Recovery Time | TSTART | 2.25 | 3.5 | ms | 12 | ||
| Low-Level Input Voltage | VIL | 0.8 | V | 12 | |||
| High-Level Input Voltage | VIH | 2 | V | 12 | |||
| Low-Level Output Voltage | VOL | 0.4 | V | IOL = 8mA | 12 | ||
| Input Leakage Current | ILI | -10 | 10 | uA | 12 | ||
| Differential Receiver Common-Mode Voltage | VCMFS | 0.8 | 2.5 | V | 13 | ||
| Single-Ended Receiver Hysteresis | VHYSSE | 0.05 | 0.15 | V | 13 | ||
| High Level Output Voltage | VFSOH | 2.8 | 3.6 | V | Pull-down resistor on DP, DM; RL = 15kΩ to GND | 13 | |
| Driver Output Impedance for HS and FS | ZHSDRV | 40.5 | 45 | 49.5 | Ω | Steady state drive | 13 |
| Pull-up Resistor Impedance | ZPU | 0.9 | 1.24 | 1.575 | kΩ | Bus Idle | 13 |
| Pull-up Resistor Impedance | ZPURX | 1.425 | 2.26 | 3.09 | kΩ | Device Receiving | 13 |
| Pull-dn Resistor Impedance | ZPD | 14.25 | 15 | 15.75 | kΩ | 13 | |
| HS Data Signaling Common Mode Voltage Range | VCMHS | -50 | 500 | mV | 13 | ||
| Hi-Speed Low Level Output Voltage (DP/DM referenced to GND) | VHSOL | -10 | 10 | mV | 45Ω load | 13 | |
| Hi-Speed High Level Output Voltage (DP/DM referenced to GND) | VHSOH | 360 | 440 | mV | 45Ω load | 13 | |
| Chirp-J Output Voltage (Differential) | VCHIRPJ | 700 | 1100 | mV | HS termination resistor disabled, pull-up resistor connected. 45Ω load. | 13 | |
| Chirp-K Output Voltage (Differential) | VCHIRPK | -900 | -500 | mV | HS termination resistor disabled, pull-up resistor connected. 45Ω load. | 13 | |
| OFF-State Leakage Current | ILZ | -10 | 10 | uA | 14 | ||
| Transceiver Input Capacitance | CIN | 5 | 10 | pF | Pin to GND | 14 | |
| FS Output Driver Timing Rise Time | TFSR | 4 | 20 | ns | CL = 50pF; 10 to 90% of /VOH - VOL/ | 14 | |
| FS Output Driver Timing Fall Time | TFFF | 4 | 20 | ns | CL = 50pF; 10 to 90% of /VOH - VOL/ | 14 | |
| Output Signal Crossover Voltage | VCRS | 1.3 | 2 | V | Excluding the first transition from IDLE state | 14 | |
| Differential Rise/Fall Time Matching | FRFM | 90 | 111.1 | % | Excluding the first transition from IDLE state | 14 | |
| SessEnd trip point | VSessEnd | 0.2 | 0.5 | 0.8 | V | 14 | |
| SessVld trip point | VSessVld | 0.8 | 1.4 | 2 | V | 14 | |
| VBUSVld trip point | VVbusVld | 4.4 | 4.58 | 4.75 | V | 14 | |
| Vbus Pull-Up | RVbusPu | 281 | 340 | Ω | Vbus to VDD3.3 (ChargeVbus = 1) | 14 | |
| Vbus Pull-down | RVbusPd | 656 | 850 | Ω | Vbus to GND (DisChargeVbus = 1) | 14 | |
| Vbus Impedance | RVbus | 40 | 75 | 100 | kΩ | Vbus to GND | 14 |
| ID pull-up resistance | RIdPullUp | 80 | 100 | 120 | kΩ | IdPullup = 1 | 14 |
| STP pull-up resistance | RSTP | 240 | 330 | 600 | kΩ | InterfaceProtectDisable = 0 | 14 |
| VDDA1.8 Regulator Output Voltage | VDDA1.8 | 1.6 | 1.8 | 2 | V | Normal Operation (SuspendM = 1) | 15 |
| VDD1.8 Regulator Output Voltage | VDD1.8 | 1.6 | 1.8 | 2 | V | 15 | |
| Total Allowable PPM Budget | -500 | 500 | PPM | Note 5-1 | 15 | ||
| Equivalent Series Resistance | R1 | 30 | Ohm | 15 | |||
| Drive Level | PW | 0.5 | mW | 15 |
CAD (KiCad official)
- Symbol:
USB3300-EZK - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
usb3300-ezk-etched.step/usb3300-ezk-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);usb3300-ezk.step/usb3300-ezk.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (53 pp, sha256
33e73e37f5110cb9, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).