main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3h ago
viewers ucc5350mcdwvr: viewers · Ray 3h ago
package.json Publish 0.1.0 · Ray 3h ago
page.json Set visibility: public · Ray 3h ago
README.md Initial commit: component/ucc5350mcdwvr · Ray 3h ago
ucc5350mcdwvr-etched.glb ucc5350mcdwvr: factory component page (tier=lcsc) · Ray 3h ago
ucc5350mcdwvr-etched.step ucc5350mcdwvr: factory component page (tier=lcsc) · Ray 3h ago
ucc5350mcdwvr-hero.glb Publish 0.1.0 · Ray 3h ago
ucc5350mcdwvr-hero.overlay.json Publish 0.1.0 · Ray 3h ago
ucc5350mcdwvr.glb Publish 0.1.0 · Ray 3h ago
ucc5350mcdwvr.kicad_mod Publish 0.1.0 · Ray 3h ago
ucc5350mcdwvr.kicad_sym Publish 0.1.0 · Ray 3h ago
ucc5350mcdwvr.lbr Publish 0.1.0 · Ray 3h ago
ucc5350mcdwvr.step Publish 0.1.0 · Ray 3h ago

UCC5350MCDWVR

Texas Instruments · Isolators - Gate Drivers · SOIC-8

UCC5350MCDWVR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC1 power_in Input-side power supply voltage from 3V to 15V with integrated UVLO protection; connect low ESR/ESL decoupling capacitor to GND1.
2 IN+ input Non-inverting gate drive voltage control input with CMOS threshold (0.55×VCC1 typical high, 0.45×VCC1 typical low), internal pull-down to low when left open, and negative 5V input voltage tolerance.
3 IN- input Inverting gate drive voltage control input with CMOS threshold, internal pull-up to high when left open, and negative 5V input voltage tolerance.
4 GND1 power_in Input-side ground reference serving common return for all input signals and connection point for VCC1 decoupling capacitor.
5 VCC2 power_in Output-side positive power supply from 9.5V to 33V with integrated UVLO protection; connect low ESR/ESL decoupling capacitor to VEE2.
6 OUT output Gate drive output for Miller clamp configuration with 10A typical source current and 10A typical sink current, 12Ω pull-up and 0.26Ω pull-down on-resistance, switching between VCC2 and VEE2 rails.
7 CLAMP input Active Miller clamp input for preventing false turn-on of power switch by clamping gate voltage to approximately 2V below VCC2 to sink Miller current.
8 VEE2 power_in Output-side ground (GND for M version) serving as negative rail return for gate driver output stage; connect low ESR/ESL decoupling capacitor to VCC2.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

CAD (KiCad official)

  • Symbol: UCC5350MCDWVR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ucc5350mcdwvr-etched.step / ucc5350mcdwvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc5350mcdwvr.step / ucc5350mcdwvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (57 pp, sha256 84c7492975118783, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF