UCC38C41DR

Texas Instruments · AC-DC Controllers And Regulators · SOIC-8

UCC38C41DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COMP	output	Error amplifier output for loop compensation, internally current limited so that zero duty cycle can be commanded by forcing COMP to GND, with a 10 mA maximum sink current rating.
2	FB	input	Inverting input of the error amplifier, whose non-inverting input is internally trimmed to 2.5 V ±1%.
3	CS	input	Primary-side current sense input to the PWM comparator, connected to the MOSFET source sense resistor, with a typical current sense amplifier gain of 3 V/V and an RC filter that may be needed against leading-edge noise.
4	RT/CT	bidirectional	Oscillator set point, where timing resistor RRT is connected to VREF and timing capacitor CCT to GND to set the switching frequency, with the maximum operating frequency stated as 1 MHz.
5	GND	power_in	Ground return pin for the output driver stage and the logic-level controller section, to which all voltages are referenced.
6	OUT	output	Totem-pole drive output intended to drive a MOSFET directly, sourcing and sinking up to 1 A peak; on the UCC38C41 the output runs at one-half the oscillator frequency, limiting maximum duty cycle to less than 50%.
7	VDD	power_in	Power input for the device with an absolute maximum of 20 V, requiring a 0.1 µF ceramic bypass capacitor to GND placed as close as possible to the pin.
8	VREF	power_in	5 V reference output (±1% tolerance) that must be bypassed to GND with a ceramic capacitor of at least 0.1 µF placed close to the pin, with a 55 mA maximum short-circuit current.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

CAD (KiCad official)

Symbol: UCC38C41DR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ucc38c41dr-etched.step / ucc38c41dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc38c41dr.step / ucc38c41dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (60 pp, sha256 9fa55f996731c56b, retrieved 2026-10-08, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# UCC38C41DR

**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-8

UCC38C41DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for loop compensation, internally current limited so that zero duty cycle can be commanded by forcing COMP to GND, with a 10 mA maximum sink current rating. |
| 2 | FB | input | Inverting input of the error amplifier, whose non-inverting input is internally trimmed to 2.5 V ±1%. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator, connected to the MOSFET source sense resistor, with a typical current sense amplifier gain of 3 V/V and an RC filter that may be needed against leading-edge noise. |
| 4 | RT/CT | bidirectional | Oscillator set point, where timing resistor RRT is connected to VREF and timing capacitor CCT to GND to set the switching frequency, with the maximum operating frequency stated as 1 MHz. |
| 5 | GND | power_in | Ground return pin for the output driver stage and the logic-level controller section, to which all voltages are referenced. |
| 6 | OUT | output | Totem-pole drive output intended to drive a MOSFET directly, sourcing and sinking up to 1 A peak; on the UCC38C41 the output runs at one-half the oscillator frequency, limiting maximum duty cycle to less than 50%. |
| 7 | VDD | power_in | Power input for the device with an absolute maximum of 20 V, requiring a 0.1 µF ceramic bypass capacitor to GND placed as close as possible to the pin. |
| 8 | VREF | power_in | 5 V reference output (±1% tolerance) that must be bypassed to GND with a ceramic capacitor of at least 0.1 µF placed close to the pin, with a 55 mA maximum short-circuit current. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## CAD (KiCad official)

- Symbol: `UCC38C41DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ucc38c41dr-etched.step` / `ucc38c41dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc38c41dr.step` / `ucc38c41dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ucc38c41.pdf) (60 pp, sha256 `9fa55f996731c56b`, retrieved 2026-10-08, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ucc38c41dr-datasheet.pdf)