component
UCC3580DTR-3
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 21d ago |
| viewers | 21d ago |
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| README.md | 17d ago |
| ucc3580dtr-3-etched.glb | 21d ago |
| ucc3580dtr-3-etched.step | 21d ago |
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| ucc3580dtr-3-hero.overlay.json | 21d ago |
| ucc3580dtr-3.glb | 21d ago |
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| ucc3580dtr-3.step | 21d ago |
UCC3580DTR-3
Texas Instruments · DC-DC Converters · SOIC-16
UCC3580DTR-3 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DELAY | passive | A resistor from DELAY to GND programs the nonoverlap delay between OUT1 and OUT2 (Delay1 and Delay2). |
| 2 | LINE | input | Hysteretic comparator input with thresholds of 5.0V and 4.5V, used to sense input line voltage and turn off OUT1 when the line is low. |
| 3 | VDD | power_in | Chip power supply pin, bypassed to PGND, with a 15V shunt clamp to GND (sinks up to 10mA); the -3 version starts above 9V and runs above 8.5V. |
| 4 | OUT1 | output | Gate drive output for the main switch, capable of sourcing up to 0.5A and sinking 1A. |
| 5 | PGND | power_in | Ground connection for the gate drivers, connected to GND at a single point so no high frequency switching currents flow in the ground plane. |
| 6 | OUT2 | output | Gate drive output for the auxiliary switch with 0.3A drive current capability; inverted (drives NMOS) in the -3 version. |
| 7 | CLK | output | Oscillator clock output from a low impedance CMOS driver, high during guaranteed off time, and able to synchronize up to five other UCC3580 PWMs. |
| 8 | GND | power_in | Signal ground. |
| 9 | RAMP | input | Feedforward ramp input programmed by a resistor R4 to input voltage and capacitor CR to GND; the flux comparator limits it at 3.3V (volt-second clamp = 3.3 x R4 x CR). |
| 10 | OSC2 | passive | Oscillator programming pin; a resistor to the timing capacitor controls guaranteed off time and, together with OSC1, sets frequency. |
| 11 | OSC1 | passive | Oscillator programming pin; a resistor to the timing capacitor sets maximum on time and, together with OSC2, sets frequency. |
| 12 | EAOUT | output | Error amplifier output and input to the PWM comparator, where loop compensation components connect from EAOUT to EAIN. |
| 13 | EAIN | input | Inverting input to the error amplifier (noninverting input internally set to 2.5V), used for feedback and loop compensation. |
| 14 | REF | power_out | Precision 5.0V reference that can supply up to 5mA to external circuits, bypassed to GND with a 1uF capacitor. |
| 15 | SS | passive | A capacitor from SS to ground programs the soft start time; EAOUT follows the SS ramp until regulation is achieved. |
| 16 | SHTDWN | input | Comparator input with 0.5V threshold that stops the chip, forcing OUT1 low while OUT2 continues to oscillate. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Frequency | 370 | 400 | 430 | kHz | 3 | ||
| CLK Pulse Width | 650 | 750 | 850 | ns | 3 | ||
| CLK VOH | 4.3 | 4.7 | V | ICLK = 3 mA | 3 | ||
| CLK VOL | 0.3 | 0.5 | V | ICLK = 3 mA | 3 | ||
| Ramp VOL | 50 | 100 | mV | IRAMP = 100 uA | 3 | ||
| Flux Comparator Vth | 3.16 | 3.33 | 3.5 | V | 3 | ||
| Maximum Duty Cycle | 63 | 66 | 69 | % | OUT1, EAIN = 2.6 V | 3 | |
| PWM Comparator Offset | 0.1 | 0.4 | 0.9 | V | 3 | ||
| EAIN | EAIN | 2.44 | 2.5 | 2.56 | V | EAOUT = EAIN | 3 |
| IEAIN | IEAIN | 150 | 400 | nA | EAOUT = EAIN | 3 | |
| EAOUT VOL | 0.3 | 0.5 | V | EAIN = 2.6 V, IEAOUT = 100 uA | 3 | ||
| EAOUT VOH | 4 | 5 | 5.5 | V | EAIN = 2.4 V, IEAOUT = 100 uA | 3 | |
| AVOL | AVOL | 70 | 80 | dB | 3 | ||
| Gain Bandwidth Product | 2 | 6 | MHz | f = 100 kHz (Note 1) | 3 | ||
| SS VOL | 100 | 350 | mV | ISS = 100 uA | 3 | ||
| SS Restart Threshold | 400 | 550 | mV | 3 | |||
| ISS | ISS | -35 | -20 | uA | 3 | ||
| SHTDWN VTH | 0.4 | 0.5 | 0.6 | V | 3 | ||
| ISHTDWN | ISHTDWN | 50 | 150 | nA | 3 | ||
| VDD On (UCC3580-1,-3) | VDD | 8 | 9 | 10 | V | 3 | |
| VDD Off | VDD | 7.5 | 8.5 | 9.5 | V | 3 | |
| LINE On | LINE | 4.7 | 5 | 5.3 | V | 3 | |
| LINE Off | LINE | 4.2 | 4.5 | 4.8 | V | 3 | |
| ILINE | ILINE | 50 | 150 | nA | LINE = 6 V | 3 | |
| VDD Clamp | VDD | 14 | 15 | 16 | V | IVDD = 10 mA | 3 |
| IVDD Start | IVDD | 160 | 250 | uA | VDD < VDD On | 3 | |
| IVDD Operating | IVDD | 2.5 | 3.5 | mA | No Load | 3 | |
| OUT1 VSAT High | 0.4 | 1 | V | IOUT1 = 50 mA | 3 | ||
| OUT1 VSAT Low | 0.4 | 1 | V | IOUT1 = 100 mA | 3 | ||
| OUT2 VSAT High | 0.4 | 1 | V | IOUT2 = 30 mA | 3 | ||
| OUT2 VSAT Low | 0.4 | 1 | V | IOUT2 = 30 mA | 3 | ||
| OUT1 Fall Time | 20 | 50 | ns | COUT1 = 1nF, RS = 3 | 3 | ||
| OUT1 Rise Time | 40 | 80 | ns | COUT1 = 1nF, RS = 3 | 3 | ||
| OUT2 Fall Time | 20 | 50 | ns | COUT2 = 300pF, RS = 10 | 3 | ||
| OUT2 Rise Time | 20 | 40 | ns | COUT2 = 300pF, RS = 10 | 3 | ||
| Delay 1 OUT2 to OUT1 | 90 | 120 | 160 | ns | R3 = 100 k, COUT1 = COUT2 = 15 pF | 4 | |
| Delay 1 OUT2 to OUT1 (TA = TJ = 25 C) | 100 | 120 | 140 | ns | TA = TJ = 25°C | 4 | |
| Delay 2 OUT1 to OUT2 | 110 | 170 | 250 | ns | R3 = 100 k, COUT1 = COUT2 = 15 pF | 4 | |
| Delay 2 OUT1 to OUT2 (TA = TJ = 25 C) | 140 | 170 | 200 | ns | TA = TJ = 25°C | 4 | |
| REF | REF | 4.875 | 5 | 5.125 | V | IREF = 0 | 4 |
| Load Regulation | 1 | 20 | mV | IREF = 0 mA to 1 mA | 4 | ||
| Line Regulation | 1 | 20 | mV | VDD = 10 V to 14 V | 4 | ||
| VDD | VDD | 16 | V | 2 | |||
| IVDD | IVDD | 25 | mA | 2 | |||
| LINE, RAMP | LINE, RAMP | -0.3 | V | upper limit printed as VDD + 1 V | 2 | ||
| ILINE, IRAMP | ILINE, IRAMP | 5 | mA | 2 | |||
| DELAY | DELAY | 5.3 | V | 2 | |||
| IDELAY | IDELAY | 5 | mA | 2 | |||
| IOUT1 | IOUT1 | -0.6 | 1.2 | A | tpw < 1 s and Duty Cycle < 10% | 2 | |
| IOUT2 | IOUT2 | -0.4 | 0.4 | A | tpw < 1 s and Duty Cycle < 10% | 2 | |
| ICLK | ICLK | -100 | 100 | mA | 2 | ||
| OSC1, OSC2, SS, SHTDWN, EAIN | OSC1, OSC2, SS, SHTDWN, EAIN | -0.3 | V | upper limit printed as REF + 0.3 V | 2 | ||
| IEAOUT | IEAOUT | -5 | 5 | mA | 2 | ||
| IREF | IREF | 30 | mA | 2 | |||
| PGND | PGND | -0.2 | 0.2 | V | 2 | ||
| Storage Temperature | -65 | 150 | °C | 2 | |||
| Junction Temperature | -55 | 150 | °C | 2 | |||
| Lead Temperature | 300 | °C | Soldering, 10 sec. | 2 | |||
| Ambient Operating Temperature (UCC3580) | TA | 0 | 70 | °C | 2 |
CAD (KiCad official)
- Symbol:
UCC3580DTR-3 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
ucc3580dtr-3-etched.step/ucc3580dtr-3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc3580dtr-3.step/ucc3580dtr-3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (16 pp, sha256
22578373a5379f7a, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).