# UCC2895QDWRQ1

**Texas Instruments** · DC-DC Converters · SOIC-20-300mil

UCC2895QDWRQ1 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EAN | input | Inverting input to the error amplifier, which must be kept below 3.6 V for proper operation. |
| 2 | EAOUT | bidirectional | Error amplifier output, internally clamped to the soft-start voltage and feeding the PWM and no-load comparators, which shut the outputs down below 500 mV and re-enable them above 600 mV. |
| 3 | RAMP | input | Inverting input of the PWM comparator, receiving the CT waveform in voltage or average-current mode or the current signal plus slope compensation in peak-current mode. |
| 4 | REF | output | 5-V ±1.2% reference that can supply up to 5 mA to external loads, with no more than 1 µF of total capacitance on this pin. |
| 5 | GND | power_in | Ground for all circuits except the output stages, and must be electrically tied to PGND. |
| 6 | SYNC | bidirectional | Oscillator synchronization pin that outputs the internal clock or accepts an external clock, with a level-sensitive input threshold of 1.9 V low and 2.1 V high. |
| 7 | CT | input | Oscillator timing capacitor charged by a programmed current to a 2.35 V sawtooth peak, with CT ranging from 100 pF to 880 pF. |
| 8 | RT | input | Oscillator timing resistor that sets the switching frequency, with RT ranging from 40 kΩ to 120 kΩ. |
| 9 | DELAB | input | Programs the dead time between OUTA and OUTB, can source approximately 1 mA maximum, is clamped to a minimum of 0.5 V, and tying it to REF defeats the programmed delay. |
| 10 | DELCD | input | Programs the dead time between OUTC and OUTD, can source approximately 1 mA maximum, is clamped to a minimum of 0.5 V, and tying it to REF defeats the programmed delay. |
| 11 | ADS | input | Adaptive delay set input, which must be limited to between 0 V and 2.5 V and must be less than or equal to CS. |
| 12 | CS | input | Current-sense input for cycle-by-cycle current limiting, with an overcurrent threshold of 2.5 V that initiates a soft stop. |
| 13 | OUTD | output | 100-mA CMOS driver output for the second half-bridge, phase shifted with respect to OUTB. |
| 14 | OUTC | output | 100-mA CMOS driver output for the second half-bridge, phase shifted with respect to OUTA. |
| 15 | VDD | power_in | Power-supply input that must be bypassed with a minimum of 1 µF low-ESR, low-ESL capacitor to ground. |
| 16 | PGND | power_in | Output-stage power ground that carries high current, so its board traces must be low impedance and electrically tied to GND. |
| 17 | OUTB | output | 100-mA CMOS driver output for the first half-bridge, fully complementary to OUTA assuming no programmed delay. |
| 18 | OUTA | output | 100-mA CMOS driver output for the first half-bridge, operating near 50% duty cycle at one-half the oscillator frequency. |
| 19 | SS/DISB | input | Combined soft-start and disable pin, where forcing it below 0.5 V disables the chip and it sources current equal to IRT during soft start. |
| 20 | EAP | input | Noninverting input to the error amplifier, which must be kept below 3.6 V for proper operation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Power Management (PMIC) |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range (EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB), lower limit |  | -0.3 |  |  | V | Upper limit printed as REF + 0.3 V | 2 |
| Drive output voltage range (OUTA, OUTB, OUTC, OUTD), lower limit |  | -0.3 |  |  | V | Upper limit printed as VDD + 0.3 V | 2 |
| Supply voltage | VDD |  |  | 17 | V | IDD < 10 mA | 2 |
| Supply current | IDD |  |  | 30 | mA |  | 2 |
| Reference current | IREF |  |  | 15 | mA |  | 2 |
| Output current | IO |  |  | 100 | mA |  | 2 |
| Power dissipation | PD |  |  | 650 | mW | TA = 25°C | 2 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 2 |
| Junction temperature range | TJ | -55 |  | 150 | °C |  | 2 |
| Electrostatic discharge protection, human-body model (HBM) |  |  |  | 800 | V | Human-body model (HBM) | 2 |
| Supply voltage | VDD | 10 |  | 16.5 | V |  | 2 |
| Reference bypass capacitor | CREF | 0.1 |  | 4.7 | μF |  | 2 |
| Delay resistor | RDEL_AB, RDEL_CD | 2.5 |  | 40 | kΩ |  | 3 |
| Operating junction temperature | TJ | -55 |  | 125 | °C |  | 3 |
| Start-up voltage threshold | UVLO(on) | 10.2 | 11 | 11.8 | V |  | 3 |
| Minimum operating voltage after start-up | UVLO(off) | 8.2 | 9 | 9.8 | V |  | 3 |
| Hysteresis | UVLO(hys) | 1 | 2 | 3 | V |  | 3 |
| Start-up current | ISTART | 150 |  | 250 | μA | VDD = 8 V | 3 |
| Operating current | IDD | 5 |  | 6 | mA |  | 3 |
| VDD clamp voltage | VDD_CLAMP | 16.5 | 17.5 | 18.5 | V | IDD = 10 mA | 3 |
| Output voltage | VREF | 4.94 | 5 | 5.06 | V | TJ = 25°C | 3 |
| Output voltage | VREF | 4.85 | 5 | 5.15 | V | 10 V < VDD < VDD_CLAMP, 0 mA < IREF < 5 mA, TJ = –40°C to 125°C | 3 |
| Short-circuit current | ISC | 10 |  | 20 | mA | REF = 0 V, TJ = 25°C | 3 |
| Common-mode input voltage |  | -0.1 |  | 3.6 | V |  | 3 |
| Offset voltage | VIO | -7 |  | 7 | mV |  | 3 |
| High-level output voltage | VOH_EAOUT | 4 | 4.5 | 5 | V | EAP – EAN = 500 mV, IEAOUT = –0.5 mA | 3 |
| Low-level output voltage | VOL_EAOUT | 0 | 0.2 | 0.4 | V | EAP – EAN = –500 mV, IEAOUT = 0.5 mA | 3 |
| Error amplifier output source current | ISOURCE | 1 |  | 1.5 | mA | EAP – EAN = 500 mV, EAOUT = 2.5 V | 3 |
| Error amplifier output sink current | ISINK | 2.5 |  | 4.5 | mA | EAP – EAN = –500 mV, EAOUT = 2.5 V | 3 |
| Open-loop dc gain | AVOL | 75 |  | 85 | dB |  | 3 |
| Unity gain bandwidth | GBW | 5 |  | 7 | MHz |  | 3 |
| Slew rate |  | 1.5 |  | 2.2 | V/μs | 1 V < EAN < 0 V, EAP = 500 mV, 0.5 V < EAOUT < 3 V | 3 |
| No-load comparator turn-off threshold |  | 0.45 | 0.5 | 0.55 | V |  | 3 |
| No-load comparator turn-on threshold |  | 0.55 | 0.6 | 0.69 | V |  | 3 |
| No-load comparator hysteresis |  | 0.035 | 0.1 | 0.165 | V |  | 3 |
| Frequency | fOSC | 473 | 500 | 527 | kHz | TJ = 25°C | 3 |
| Frequency total variation |  |  | 2.5 | 5 | % | Over line and temperature | 3 |
| High-level input voltage, SYNC | VOH_SYNC | 4.1 | 4.5 | 5 | V | ISYNC = –400 μA, VCT = 2.6 V | 3 |
| SYNC output pulse width |  | 85 |  | 135 | ns | LOADSYNC = 3.9 kΩ and 30 pF in parallel | 3 |
| Timing resistor voltage | VRT | 2.9 | 3 | 3.1 | V |  | 3 |
| Timing capacitor peak voltage | VCT(peak) | 2.25 | 2.35 | 2.55 | V |  | 3 |
| Timing capacitor valley voltage | VCT(valley) | 0 | 0.2 | 0.4 | V |  | 3 |
| Peak current threshold |  | 1.9 | 2 | 2.1 | V |  | 4 |
| Overcurrent threshold |  | 2.4 | 2.5 | 2.6 | V |  | 4 |
| Current sense to output delay |  | 75 |  | 110 | ns | 0 V ≤ CS ≤ 2.3 V, DELAB = DELCD = REF | 4 |
| Soft-start source current | ISOURCE | -40 | -35 | -30 | μA | SS/DISB = 3 V, CS = 1.9 V | 5 |
| Soft-start sink current | ISINK | 325 | 350 | 375 | μA | SS/DISB = 3 V, CS = 2.6 V | 5 |
| Soft-start/disable comparator threshold |  | 0.44 | 0.5 | 0.56 | V |  | 5 |
| DELAB/DELCD output voltage | V | 0.45 | 0.5 | 0.55 | V | ADS = CS = 0 V | 5 |
| DELAB/DELCD output voltage | V | 1.9 | 2 | 2.1 | V | ADS = 0 V, CS = 2 V | 5 |
| Output delay | tDELAY | 450 | 560 | 620 | ns | ADS = CS = 0 V | 5 |
| High-level output voltage (all outputs) | VOH | 250 |  | 420 | mV | IOUT = –10 mA, VDD to output | 5 |
| Low-level output voltage (all outputs) | VOL | 150 |  | 270 | mV | IOUT = 10 mA | 5 |
| Rise time | tR | 20 | 35 | 35 | ns | CLOAD = 100 pF | 5 |
| Fall time | tF | 20 | 35 | 35 | ns | CLOAD = 100 pF | 5 |
| EAOUT to RAMP input offset voltage |  | 0.7 | 0.85 | 1.05 | V | RAMP = 0 V, DELAB = DELCD = REF | 6 |
| Minimum phase shift |  | 0 | 0.85 | 1.5 | % | RAMP = 0 V, EAOUT = 650 mV (OUTA to OUTC, OUTB to OUTD) | 6 |
| Delay | tDELAY | 70 | 120 | 120 | ns | 0 V < RAMP < 2.5 V, EAOUT = 1.2 V, DELAB = DELCD = REF | 6 |
| RAMP bias current | IR(bias) | -5 |  | 5 | μA | RAMP < 5 V, CT = 2.2 V | 6 |
| RAMP sink current | IR(sink) | 11 | 19 | 19 | mA | RAMP = 5 V, CT = 2.6 V | 6 |

## CAD (KiCad official)

- Symbol: `UCC2895QDWRQ1`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `ucc2895qdwrq1-etched.step` / `ucc2895qdwrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ucc2895qdwrq1.step` / `ucc2895qdwrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ucc2895-q1) (25 pp, sha256 `5b333e1d4ff20c03`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ucc2895qdwrq1-datasheet.pdf)