UCC28070DWR

{
  "slug": "ucc28070dwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments AC-DC Controllers & Regulators, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management ics",
    "ucc28070dwr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ucc28070dwr.kicad_sym",
    "ucc28070dwr.kicad_mod",
    "ucc28070dwr.glb",
    "ucc28070dwr.step",
    "ucc28070dwr.lbr",
    "docs/hero.png",
    "docs/ucc28070dwr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ucc28070dwr-hero.glb",
    "ucc28070dwr-hero.overlay.json",
    "ucc28070dwr-etched.glb"
  ],
  "component": {
    "mpn": "UCC28070DWR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-20-300mil",
    "pin_count": 20,
    "category": "Power Management ICs",
    "subcategory": "AC-DC Controllers & Regulators",
    "datasheet": "https://www.ti.com/lit/ds/symlink/ucc28070dwr.pdf",
    "parts": {
      "symbol": "ucc28070dwr.kicad_sym",
      "footprint": "ucc28070dwr.kicad_mod",
      "model_3d": "ucc28070dwr-hero.glb",
      "model_3d_plain": "ucc28070dwr-etched.glb",
      "model_3d_step": "ucc28070dwr-etched.step",
      "model_3d_step_plain": "ucc28070dwr.step",
      "lbr": "ucc28070dwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C601654"
    },
    "distributor_check": {
      "checked_at": "2026-10-22T22:08:02Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CDR",
        "type": "input",
        "description": "Dither rate capacitor pin: an external capacitor to GND programs the oscillator dither rate, and connecting CDR to VREF disables dithering."
      },
      {
        "number": "2",
        "name": "RDM",
        "type": "input",
        "description": "Dither magnitude resistor and external sync pin: a resistor to GND programs the dither magnitude (30 kΩ to 330 kΩ recommended), and with dithering disabled (CDR > 5 V) the master clock synchronizes to positive edges on RDM; connect to GND if dithering and sync are unused."
      },
      {
        "number": "3",
        "name": "VAO",
        "type": "output",
        "description": "Voltage error amplifier transconductance output, connected internally to the multiplier input and zero-power comparator, with voltage loop compensation connected between this pin and GND."
      },
      {
        "number": "4",
        "name": "VSENSE",
        "type": "input",
        "description": "Output voltage sense input to the voltage error amplifier inverting input, current synthesis difference amplifier, OVP, PFC enable and slew-rate comparators, connected to the PFC output through a resistor divider."
      },
      {
        "number": "5",
        "name": "VINAC",
        "type": "input",
        "description": "Scaled AC line input voltage to the multiplier and current synthesis difference amplifier (0 V to 3 V recommended), using a resistor divider identical to the VSENSE divider."
      },
      {
        "number": "6",
        "name": "IMO",
        "type": "output",
        "description": "Multiplier current output, with a resistor to GND setting the multiplier gain (0 V to 3.3 V recommended range)."
      },
      {
        "number": "7",
        "name": "RSYNTH",
        "type": "input",
        "description": "Current synthesis down-slope programming pin: a resistor to GND (15 kΩ to 750 kΩ) sets the down-slope, and connecting it to VREF disables current synthesis."
      },
      {
        "number": "8",
        "name": "CSB",
        "type": "input",
        "description": "Phase B current sense input, internally connected to the phase B current amplifier inverting input through the current synthesis stage during GDB on-time (0 V to 3.6 V recommended)."
      },
      {
        "number": "9",
        "name": "CSA",
        "type": "input",
        "description": "Phase A current sense input, internally connected to the phase A current amplifier inverting input through the current synthesis stage during GDA on-time (0 V to 3.6 V recommended)."
      },
      {
        "number": "10",
        "name": "PKLMT",
        "type": "input",
        "description": "Peak current limit programming pin: a resistor divider from VREF sets the threshold of the cycle-by-cycle peak current limit comparators."
      },
      {
        "number": "11",
        "name": "CAOB",
        "type": "output",
        "description": "Phase B transconductance current amplifier output, connected internally to the phase B PWM comparator inverting input, with current loop compensation between this pin and GND."
      },
      {
        "number": "12",
        "name": "CAOA",
        "type": "output",
        "description": "Phase A transconductance current amplifier output, connected internally to the phase A PWM comparator inverting input, with current loop compensation between this pin and GND."
      },
      {
        "number": "13",
        "name": "VREF",
        "type": "power_in",
        "description": "6-V reference and internal bias output (5.82 V to 6.18 V, 2 mA max load) requiring a 0.1-μF ceramic bypass capacitor to GND."
      },
      {
        "number": "14",
        "name": "GDA",
        "type": "output",
        "description": "Phase A limited-current gate drive output for an external gate-drive device, typically clamped to 13.5 V."
      },
      {
        "number": "15",
        "name": "VCC",
        "type": "power_in",
        "description": "Bias voltage input (VUVLO + 1 V to 21 V recommended, 22 V absolute max) requiring a 0.1-μF ceramic bypass capacitor to GND placed close to the pin."
      },
      {
        "number": "16",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground reference for all compensation and programming networks, to be connected to the system through a separate trace for high-current noise isolation."
      },
      {
        "number": "17",
        "name": "GDB",
        "type": "output",
        "description": "Phase B limited-current gate drive output for an external gate-drive device, typically clamped to 13.5 V."
      },
      {
        "number": "18",
        "name": "SS",
        "type": "input",
        "description": "Soft-start and external fault interface: a capacitor to GND sets the soft-start slew rate from a 10-μA source, and pulling the pin below 0.6 V immediately disables GDA and GDB."
      },
      {
        "number": "19",
        "name": "RT",
        "type": "input",
        "description": "Timing resistor pin: a resistor to GND sets the internal oscillator running frequency."
      },
      {
        "number": "20",
        "name": "DMAX",
        "type": "input",
        "description": "Maximum duty-cycle programming pin: a resistor to GND sets the maximum PWM duty cycle based on the ratio RDMX / RRT."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Datasheet lists GND as I/O; classified as power_in per ground convention. VCC type taken as power_in"
        ],
        "pages_sent": 8,
        "cost_usd": 0.1176,
        "at": "2026-10-22T22:07:36"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/ucc28070dwr.pdf",
        "pages": 49,
        "sha256": "3bd2b3b04b050fd6",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ucc28070dwr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.3,
          12.8,
          2.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",
        "checked": "2026-10-22",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ucc28070dwr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          10.3,
          12.8,
          2.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "315ddc88ffe55366f1fef8799f12721eb32c873371c497b2dde1e1fec3d72c86",
        "checked": "2026-10-22",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}