component
UCC28070DWR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers & Regulators, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC28070DWR
Texas Instruments · AC-DC Controllers & Regulators · SOIC-20-300mil
UCC28070DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CDR | input | Dither rate capacitor pin: an external capacitor to GND programs the oscillator dither rate, and connecting CDR to VREF disables dithering. |
| 2 | RDM | input | Dither magnitude resistor and external sync pin: a resistor to GND programs the dither magnitude (30 kΩ to 330 kΩ recommended), and with dithering disabled (CDR > 5 V) the master clock synchronizes to positive edges on RDM; connect to GND if dithering and sync are unused. |
| 3 | VAO | output | Voltage error amplifier transconductance output, connected internally to the multiplier input and zero-power comparator, with voltage loop compensation connected between this pin and GND. |
| 4 | VSENSE | input | Output voltage sense input to the voltage error amplifier inverting input, current synthesis difference amplifier, OVP, PFC enable and slew-rate comparators, connected to the PFC output through a resistor divider. |
| 5 | VINAC | input | Scaled AC line input voltage to the multiplier and current synthesis difference amplifier (0 V to 3 V recommended), using a resistor divider identical to the VSENSE divider. |
| 6 | IMO | output | Multiplier current output, with a resistor to GND setting the multiplier gain (0 V to 3.3 V recommended range). |
| 7 | RSYNTH | input | Current synthesis down-slope programming pin: a resistor to GND (15 kΩ to 750 kΩ) sets the down-slope, and connecting it to VREF disables current synthesis. |
| 8 | CSB | input | Phase B current sense input, internally connected to the phase B current amplifier inverting input through the current synthesis stage during GDB on-time (0 V to 3.6 V recommended). |
| 9 | CSA | input | Phase A current sense input, internally connected to the phase A current amplifier inverting input through the current synthesis stage during GDA on-time (0 V to 3.6 V recommended). |
| 10 | PKLMT | input | Peak current limit programming pin: a resistor divider from VREF sets the threshold of the cycle-by-cycle peak current limit comparators. |
| 11 | CAOB | output | Phase B transconductance current amplifier output, connected internally to the phase B PWM comparator inverting input, with current loop compensation between this pin and GND. |
| 12 | CAOA | output | Phase A transconductance current amplifier output, connected internally to the phase A PWM comparator inverting input, with current loop compensation between this pin and GND. |
| 13 | VREF | power_in | 6-V reference and internal bias output (5.82 V to 6.18 V, 2 mA max load) requiring a 0.1-μF ceramic bypass capacitor to GND. |
| 14 | GDA | output | Phase A limited-current gate drive output for an external gate-drive device, typically clamped to 13.5 V. |
| 15 | VCC | power_in | Bias voltage input (VUVLO + 1 V to 21 V recommended, 22 V absolute max) requiring a 0.1-μF ceramic bypass capacitor to GND placed close to the pin. |
| 16 | GND | power_in | Device ground reference for all compensation and programming networks, to be connected to the system through a separate trace for high-current noise isolation. |
| 17 | GDB | output | Phase B limited-current gate drive output for an external gate-drive device, typically clamped to 13.5 V. |
| 18 | SS | input | Soft-start and external fault interface: a capacitor to GND sets the soft-start slew rate from a 10-μA source, and pulling the pin below 0.6 V immediately disables GDA and GDB. |
| 19 | RT | input | Timing resistor pin: a resistor to GND sets the internal oscillator running frequency. |
| 20 | DMAX | input | Maximum duty-cycle programming pin: a resistor to GND sets the maximum PWM duty cycle based on the ratio RDMX / RRT. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Power Management ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 22 | V | 4 | |||
| Supply current | IVCC | 20 | mA | 4 | |||
| Gate drive current continuous | GDA, GDB | -0.25 | 0.25 | A | 4 | ||
| Gate drive current pulsed | GDA, GDB | -0.75 | 0.75 | A | 4 | ||
| Voltage GDA, GDB | -0.5 | V | max VCC + 0.3 V | 4 | |||
| Voltage DMAX, RDM, RT, CDR, VINAC, VSENSE, SS, VAO, IMO, CSA, CSB, CAOA, CAOB, PKLMT, VREF | -0.5 | 7 | V | 4 | |||
| Lead temperature | 260 | °C | 10 seconds | 4 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | 2000 | V | Human-body model per ANSI/ESDA/JEDEC JS-001 | 4 | ||
| ESD CDM | V(ESD) | 500 | V | Charged-device model per JESD22-C101 | 4 | ||
| VCC input voltage | VCC | 21 | V | from a low-impedance source; min VUVLO + 1 V | 5 | ||
| Load current VREF | 2 | mA | 5 | ||||
| Input voltage range VINAC | 0 | 3 | V | 5 | |||
| Voltage range IMO | 0 | 3.3 | V | 5 | |||
| Voltage range CSA, CSB | VPKLMT | 0 | 3.6 | V | 5 | ||
| RSYNTH resistance | RSYN | 15 | 750 | kΩ | 5 | ||
| RDM resistance | RRDM | 30 | 330 | kΩ | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 78.1 | °C/W | SOIC (DW) 20 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 42.5 | °C/W | SOIC (DW) 20 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 46 | °C/W | SOIC (DW) 20 pins | 5 | ||
| Junction-to-top characterization parameter | ψJT | 17.5 | °C/W | SOIC (DW) 20 pins | 5 | ||
| Junction-to-board characterization parameter | ψJB | 45.5 | °C/W | SOIC (DW) 20 pins | 5 | ||
| VCC shunt voltage | VCC(SHUNT) | 23 | 25 | 27 | V | IVCC = 10 mA | 5 |
| UVLO turnon threshold | VUVLO | 9.8 | 10.2 | 10.6 | V | Measured at VCC (rising) | 5 |
| VREF enable threshold | 7.5 | 8 | 8.5 | V | Measured at VCC (rising) | 5 | |
| Reference voltage no load | VVREF | 5.82 | 6 | 6.18 | V | IVREF = 0 mA | 5 |
| VREF load rejection | VVREF | -12 | 12 | mV | Measured as the change in VVREF (IVREF = 0 mA and -2 mA) | 5 | |
| VREF line rejection | VVREF | -12 | 12 | mV | Measured as the change in VVREF (VCC = 11 V and 20 V, IVREF = 0 μA) | 5 | |
| PFC enable threshold | VEN | 0.65 | 0.75 | 0.85 | V | Measured at VSENSE (rising) | 6 |
| Output phase shift | 179 | 180 | 181 | ° | Measured between GDA and GDB | 6 | |
| Timing regulation voltages | VDMAX, VRT, VRDM | 2.91 | 3 | 3.09 | V | Measured at DMAX, RT, and RDM | 6 |
| PWM switching frequency | fPWM | 95 | 100 | 105 | kHz | RRT = 75 kΩ, RDMX = 68.1 kΩ, VRDM = 0 V, VCDR = 6 V | 6 |
| PWM switching frequency | fPWM | 270 | 290 | 330 | kHz | RRT = 24.9 kΩ, RDMX = 22.6 kΩ, VRDM = 0 V, VCDR = 6 V | 6 |
| Duty-cycle clamp | DMAX | 92 | 95 | 98 | % | RRT = 75 kΩ, RDMX = 68.1 kΩ, VRDM = 0 V, VCDR = 6 V | 6 |
| Minimum programmable OFF-time | 50 | 150 | 250 | ns | RRT = 24.9 kΩ, RDMX = 22.6 kΩ, VRDM = 0 V, VCDR = 6 V | 6 | |
| Frequency dithering magnitude | fDM | 2 | 3 | 4 | kHz | RRDM = 316 kΩ, RRT = 75 kΩ | 6 |
| Frequency dithering magnitude | fDM | 24 | 30 | 36 | kHz | RRDM = 31.6 kΩ, RRT = 24.9 kΩ | 6 |
| VSENSE voltage | 2.97 | 3 | 3.03 | V | In regulation, TA = 25°C | 6 | |
| VSENSE voltage | 2.94 | 3 | 3.06 | V | In regulation | 6 | |
| VAO high voltage | 4.8 | 5 | 5.2 | V | VVSENSE = 2.9 V | 6 | |
| Slew-rate correction threshold | 92 | 93 | 95 | % | Measured as VVSENSE (falling) / VVSENSE (regulation) | 6 | |
| Adaptive SS disable | -30 | 0 | 30 | mV | Measured as VVSENSE, VSS | 7 | |
| OVP threshold | VOVP | 104 | 106 | 108 | % | Measured as VVSENSE (rising) / VVSENSE (regulation) | 7 |
| Gain constant | kMULT | 16 | 17 | 18 | μA | VVAO ≥ 1.5 V, TA = 25°C | 7 |
| Gain constant | kMULT | 15 | 17 | 19 | μA | VVAO ≥ 1.5 V | 7 |
| Level 1 threshold | VLVL1 | 0.6 | 0.7 | 0.8 | V | Measured at VINAC (rising) | 7 |
| Phase mismatch | -12 | 0 | 12 | mV | Measured as phase A input offset minus phase B input offset | 8 | |
| Regulation voltage | VRSYNTH | 2.91 | 3 | 3.09 | V | VVSENSE = 3 V, VVINAC = 0 V | 8 |
| Peak current limit threshold | 3.27 | 3.3 | 3.33 | V | VPKLMT = 3.30 V, measured at CSx (rising) | 8 | |
| PWM ramp amplitude | VRMP | 3.8 | 4 | 4.2 | V | 8 | |
| GDA, GDB output voltage, high, clamped | 11.5 | 13 | 15 | V | VCC = 20 V, CLOAD = 1 nF | 8 |
CAD (KiCad official)
- Symbol:
UCC28070DWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
ucc28070dwr-etched.step/ucc28070dwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28070dwr.step/ucc28070dwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (49 pp, sha256
3bd2b3b04b050fd6, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).