component
UCC28070APWR
Public Made by Adomby adom
Texas Instruments Pre-ordered Chips, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"name": "CDR",
"type": "input",
"description": "Dither rate capacitor pin; an external capacitor to GND programs the oscillator dither rate, and connecting CDR to VREF with RDM to GND disables dithering."
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{
"number": "2",
"name": "RDM",
"type": "input",
"description": "Dither magnitude resistor to GND and external sync input; when dithering is disabled (CDR > 5V) the internal master clock synchronizes to rising edges on this pin, and RDM is tied to GND with zero ohms if dithering and sync are unused."
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{
"number": "3",
"name": "VAO",
"type": "output",
"description": "Transconductance voltage error amplifier output, internally connected to the multiplier input and zero-power comparator, with voltage loop compensation connected between this pin and GND."
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{
"number": "4",
"name": "VSENSE",
"type": "input",
"description": "Output voltage sense input to the voltage error amplifier, current synthesis difference amplifier, OVP, PFC enable and slew-rate comparators, connected to the PFC output through a resistor divider."
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{
"number": "5",
"name": "VINAC",
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"description": "Scaled AC line input voltage to the multiplier and current synthesis difference amplifier, with a resistor divider identical to the one at VSENSE."
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"description": "Multiplier output current; a resistor between this pin and GND sets the multiplier gain."
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"number": "7",
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"description": "Current synthesis down-slope programming; a resistor to GND sets the down-slope rate, and connecting RSYNTH to VREF disables current synthesis."
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{
"number": "9",
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"description": "Phase-A current sense input, connected to the phase-A current amplifier inverting input through the current synthesis stage during GDA on-time unless RSYNTH is tied to VREF."
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{
"number": "10",
"name": "PKLMT",
"type": "input",
"description": "Peak current limit programming; a resistor divider from VREF to this pin sets the cycle-by-cycle peak current limit threshold."
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{
"number": "11",
"name": "CAOB",
"type": "output",
"description": "Phase-B transconductance current amplifier output to the phase-B PWM comparator inverting input, with current loop compensation connected between this pin and GND."
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{
"number": "12",
"name": "CAOA",
"type": "output",
"description": "Phase-A transconductance current amplifier output to the phase-A PWM comparator inverting input, with current loop compensation connected between this pin and GND."
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"description": "6V reference voltage and internal bias, requiring a 0.1µF ceramic bypass capacitor close to this pin and GND."
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"description": "Phase-A gate drive, a limited-current output for an external gate-drive device, typically clamped to 13.5V."
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"number": "15",
"name": "VCC",
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"description": "Bias voltage input (absolute maximum 22V) requiring a 0.1µF ceramic bypass capacitor close to this pin and GND."
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{
"number": "16",
"name": "GND",
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"description": "Device ground reference for all compensation and programming networks, connected to the system through a separate trace for high-current noise isolation."
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{
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"number": "18",
"name": "SS",
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"description": "Soft-start and external fault interface; a capacitor to GND sets soft-start with a 10µA source, and pulling below 0.6V immediately disables GDA and GDB."
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"number": "19",
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"description": "Timing resistor to GND that sets the internal oscillator running frequency."
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"name": "DMAX",
"type": "input",
"description": "Maximum duty-cycle programming; a resistor to GND sets the maximum PWM duty cycle based on the ratio RDMX/RRT."
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"name": "Input voltage to VCC",
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"name": "Supply current, enabled",
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"name": "Supply current, disabled",
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"name": "Supply current UVLO",
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"name": "Supply current UVLO",
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"name": "UVLO turnon threshold",
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"name": "VREF enable threshold",
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{
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