component
UCC28070APWR
Public Made by Adomby adom
Texas Instruments Pre-ordered Chips, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC28070APWR
Texas Instruments · Pre-ordered Chips · TSSOP-20
UCC28070APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CDR | input | Dither rate capacitor pin; an external capacitor to GND programs the oscillator dither rate, and connecting CDR to VREF with RDM to GND disables dithering. |
| 2 | RDM | input | Dither magnitude resistor to GND and external sync input; when dithering is disabled (CDR > 5V) the internal master clock synchronizes to rising edges on this pin, and RDM is tied to GND with zero ohms if dithering and sync are unused. |
| 3 | VAO | output | Transconductance voltage error amplifier output, internally connected to the multiplier input and zero-power comparator, with voltage loop compensation connected between this pin and GND. |
| 4 | VSENSE | input | Output voltage sense input to the voltage error amplifier, current synthesis difference amplifier, OVP, PFC enable and slew-rate comparators, connected to the PFC output through a resistor divider. |
| 5 | VINAC | input | Scaled AC line input voltage to the multiplier and current synthesis difference amplifier, with a resistor divider identical to the one at VSENSE. |
| 6 | IMO | output | Multiplier output current; a resistor between this pin and GND sets the multiplier gain. |
| 7 | RSYNTH | input | Current synthesis down-slope programming; a resistor to GND sets the down-slope rate, and connecting RSYNTH to VREF disables current synthesis. |
| 8 | CSB | input | Phase-B current sense input, connected to the phase-B current amplifier inverting input through the current synthesis stage during GDB on-time unless RSYNTH is tied to VREF. |
| 9 | CSA | input | Phase-A current sense input, connected to the phase-A current amplifier inverting input through the current synthesis stage during GDA on-time unless RSYNTH is tied to VREF. |
| 10 | PKLMT | input | Peak current limit programming; a resistor divider from VREF to this pin sets the cycle-by-cycle peak current limit threshold. |
| 11 | CAOB | output | Phase-B transconductance current amplifier output to the phase-B PWM comparator inverting input, with current loop compensation connected between this pin and GND. |
| 12 | CAOA | output | Phase-A transconductance current amplifier output to the phase-A PWM comparator inverting input, with current loop compensation connected between this pin and GND. |
| 13 | VREF | power_out | 6V reference voltage and internal bias, requiring a 0.1µF ceramic bypass capacitor close to this pin and GND. |
| 14 | GDA | output | Phase-A gate drive, a limited-current output for an external gate-drive device, typically clamped to 13.5V. |
| 15 | VCC | power_in | Bias voltage input (absolute maximum 22V) requiring a 0.1µF ceramic bypass capacitor close to this pin and GND. |
| 16 | GND | power_in | Device ground reference for all compensation and programming networks, connected to the system through a separate trace for high-current noise isolation. |
| 17 | GDB | output | Phase-B gate drive, a limited-current output for an external gate-drive device, typically clamped to 13.5V. |
| 18 | SS | input | Soft-start and external fault interface; a capacitor to GND sets soft-start with a 10µA source, and pulling below 0.6V immediately disables GDA and GDB. |
| 19 | RT | input | Timing resistor to GND that sets the internal oscillator running frequency. |
| 20 | DMAX | input | Maximum duty-cycle programming; a resistor to GND sets the maximum PWM duty cycle based on the ratio RDMX/RRT. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Interface ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 22 | V | over operating free-air temperature range | 5 | ||
| Supply current | IVCC | 20 | mA | 5 | |||
| Gate drive current continuous GDA, GDB | -0.25 | 0.25 | A | continuous | 5 | ||
| Gate drive current pulsed GDA, GDB | -0.75 | 0.75 | A | pulsed | 5 | ||
| Voltage on GDA, GDB | -0.5 | V | max is VCC + 0.3 | 5 | |||
| Voltage on DMAX, RDM, RT, CDR, VINAC, VSENSE, SS, VAO, IMO, CSA, CSB, CAOA, CAOB, PKLMT, VREF | -0.5 | 7 | V | 5 | |||
| Current on VREF, VAO, CAOA, CAOB, IMO | 10 | mA | 5 | ||||
| Current on RT, DMAX, RDM, RSYNTH | -0.5 | mA | 5 | ||||
| Lead temperature | 260 | °C | 10 seconds | 5 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| ESD HBM | V(ESD) | 2000 | V | ANSI/ESDA/JEDEC JS-001 | 5 | ||
| ESD CDM | V(ESD) | 500 | V | JESD22-C101 | 5 | ||
| Input voltage to VCC | VCC | 21 | V | from a low-impedance source; min is VUVLO + 1 | 6 | ||
| Load current on VREF | 2 | mA | 6 | ||||
| Input voltage to VINAC | 0 | 3 | V | 6 | |||
| Voltage on IMO | 0 | 3.3 | V | 6 | |||
| Voltage on CSA, CSB, PKLMT | 0 | 3.6 | V | 6 | |||
| RSYNTH resistance | RSYN | 15 | 750 | kΩ | 6 | ||
| RDM resistance | RRDM | 30 | 330 | kΩ | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 99.9 | °C/W | PW (TSSOP) 20 pins | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 34.1 | °C/W | PW (TSSOP) 20 pins | 6 | ||
| Junction-to-board thermal resistance | RθJB | 50.8 | °C/W | PW (TSSOP) 20 pins | 6 | ||
| Junction-to-top characterization parameter | ψJT | 1.9 | °C/W | PW (TSSOP) 20 pins | 6 | ||
| Junction-to-board characterization parameter | ψJB | 50.3 | °C/W | PW (TSSOP) 20 pins | 6 | ||
| VCC shunt voltage | VCC(SHUNT) | 23 | 25 | 27 | V | IVCC = 10mA | 7 |
| Supply current, enabled | IVCC | 9 | 12 | mA | VVSENSE = 3V (switching) | 7 | |
| Supply current, disabled | IVCC | 7 | mA | VVSENSE = 0V | 7 | ||
| Supply current UVLO | IVCC | 200 | µA | VCC = 7V | 7 | ||
| Supply current UVLO | IVCC | 4 | 6 | mA | VCC = 9V | 7 | |
| UVLO turnon threshold | VUVLO | 9.8 | 10.2 | 10.6 | V | Measured at VCC (rising) | 7 |
| VREF enable threshold | 7.5 | 8 | 8.5 | V | Measured at VCC (rising) | 7 | |
| Reference voltage | VVREF | 5.82 | 6 | 6.18 | V | No load IVREF = 0mA | 7 |
| Load rejection | -12 | 12 | mV | Change in VVREF (IVREF = 0mA and -2mA) | 7 | ||
| Line rejection | -12 | 12 | mV | VCC = 11V and 20V, IVREF = 0μA | 7 | ||
| PFC enable threshold | VEN | 0.65 | 0.75 | 0.85 | V | Measured at VSENSE (rising) | 7 |
| External PFC disable threshold | 0.5 | 0.6 | V | Measured at SS (falling) | 7 | ||
| Output phase shift | 179 | 180 | 181 | ° | Measured between GDA and GDB | 7 | |
| Timing regulation voltages | VDMAX, VRT, VRDM | 2.91 | 3 | 3.09 | V | Measured at DMAX, RT, and RDM | 7 |
| PWM switching frequency, UCC28070A only | fPWM | 9.75 | 10.25 | 10.75 | kHz | RRT = 750kΩ, RDMX = 681kΩ, VRDM = 0V, VCDR = 6V | 7 |
| PWM switching frequency | fPWM | 95 | 100 | 105 | kHz | RRT = 75kΩ, RDMX = 68.1kΩ, VRDM = 0V, VCDR = 6V | 7 |
| PWM switching frequency | fPWM | 270 | 290 | 330 | kHz | RRT = 24.9kΩ, RDMX = 22.6kΩ, VRDM = 0V, VCDR = 6V | 7 |
| Duty-cycle clamp | DMAX | 92 | 95 | 98 | % | RRT = 75kΩ, RDMX = 68.1kΩ, VRDM = 0V, VCDR = 6V | 7 |
| Minimum programmable OFF-time | 50 | 150 | 250 | ns | RRT = 24.9kΩ, RDMX = 22.6kΩ, VRDM = 0V, VCDR = 6V | 7 | |
| Frequency dithering magnitude | fDM | 2 | 3 | 4 | kHz | RRDM = 316kΩ, RRT = 75kΩ | 7 |
| Frequency dithering magnitude | fDM | 24 | 30 | 36 | kHz | RRDM = 31.6kΩ, RRT = 24.9kΩ | 7 |
| Dither disable threshold | 5 | 5.25 | V | Measured at CDR (rising) | 7 | ||
| SYNC propagation delay | 50 | 100 | ns | VCDR = 6V, RDM (rising) to GDx (rising) | 8 | ||
| SYNC threshold (rising) | 1.2 | 1.5 | V | VCDR = 6V, measured at RDM | 8 | ||
| SYNC threshold (falling) | 0.4 | 0.7 | V | VCDR = 6V, measured at RDM | 8 | ||
| SYNC pulse width, minimum | tSYNC | 0.2 | μs | Positive pulse | 8 | ||
| VSENSE voltage | 2.97 | 3 | 3.03 | V | In regulation, TA = 25°C | 8 | |
| VSENSE voltage | 2.94 | 3 | 3.06 | V | In regulation | 8 | |
| VSENSE input bias current | 250 | 500 | nA | In regulation | 8 | ||
| VAO high voltage | 4.8 | 5 | 5.2 | V | VVSENSE = 2.9V | 8 | |
| VAO low voltage | 0.05 | 0.5 | V | VVSENSE = 3.1V | 8 | ||
| Slew-rate correction threshold | 92 | 93 | 95 | % | VVSENSE (falling) / VVSENSE (regulation) | 8 | |
| Adaptive source current | -2.5 | -1.5 | mA | VVSENSE = 2V, VSS = 1V | 8 | ||
| OVP threshold | VOVP | 104 | 106 | 108 | % | VVSENSE (rising) / VVSENSE (regulation) | 8 |
| Gain constant | kMULT | 15 | 17 | 19 | μA | VVAO ≥ 1.5V | 9 |
| Peak current limit threshold | 3.27 | 3.3 | 3.33 | V | VPKLMT = 3.3V, measured at CSx (rising) | 10 | |
| GDA, GDB output voltage, high, clamped | 11.5 | 13 | 15 | V | VCC = 20V, CLOAD = 1nF | 10 | |
| Operating junction temperature (packaging addendum, UCC28070APWR) | -40 | 125 | °C | Op temp | 46 |
CAD (KiCad official)
- Symbol:
UCC28070APWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
ucc28070apwr-etched.step/ucc28070apwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28070apwr.step/ucc28070apwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (57 pp, sha256
632656aea01a2438, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).