UCC28070APWR

{
  "slug": "ucc28070apwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Pre-ordered Chips, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface ics",
    "ucc28070apwr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ucc28070apwr.kicad_sym",
    "ucc28070apwr.kicad_mod",
    "ucc28070apwr.glb",
    "ucc28070apwr.step",
    "ucc28070apwr.lbr",
    "docs/hero.png",
    "docs/ucc28070apwr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ucc28070apwr-hero.glb",
    "ucc28070apwr-hero.overlay.json",
    "ucc28070apwr-etched.glb"
  ],
  "component": {
    "mpn": "UCC28070APWR",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-20",
    "pin_count": 20,
    "category": "Interface ICs",
    "subcategory": "Pre-ordered Chips",
    "datasheet": "https://www.ti.com/lit/ds/symlink/ucc28070a.pdf",
    "parts": {
      "symbol": "ucc28070apwr.kicad_sym",
      "footprint": "ucc28070apwr.kicad_mod",
      "model_3d": "ucc28070apwr-hero.glb",
      "model_3d_plain": "ucc28070apwr-etched.glb",
      "model_3d_step": "ucc28070apwr-etched.step",
      "model_3d_step_plain": "ucc28070apwr.step",
      "lbr": "ucc28070apwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2876965",
      "digikey": "296-41051-2-ND"
    },
    "distributor_check": {
      "checked_at": "2026-10-22T18:56:36Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-41051-2-ND",
        "status": "found"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CDR",
        "type": "input",
        "description": "Dither rate capacitor pin; an external capacitor to GND programs the oscillator dither rate, and connecting CDR to VREF with RDM to GND disables dithering."
      },
      {
        "number": "2",
        "name": "RDM",
        "type": "input",
        "description": "Dither magnitude resistor to GND and external sync input; when dithering is disabled (CDR > 5V) the internal master clock synchronizes to rising edges on this pin, and RDM is tied to GND with zero ohms if dithering and sync are unused."
      },
      {
        "number": "3",
        "name": "VAO",
        "type": "output",
        "description": "Transconductance voltage error amplifier output, internally connected to the multiplier input and zero-power comparator, with voltage loop compensation connected between this pin and GND."
      },
      {
        "number": "4",
        "name": "VSENSE",
        "type": "input",
        "description": "Output voltage sense input to the voltage error amplifier, current synthesis difference amplifier, OVP, PFC enable and slew-rate comparators, connected to the PFC output through a resistor divider."
      },
      {
        "number": "5",
        "name": "VINAC",
        "type": "input",
        "description": "Scaled AC line input voltage to the multiplier and current synthesis difference amplifier, with a resistor divider identical to the one at VSENSE."
      },
      {
        "number": "6",
        "name": "IMO",
        "type": "output",
        "description": "Multiplier output current; a resistor between this pin and GND sets the multiplier gain."
      },
      {
        "number": "7",
        "name": "RSYNTH",
        "type": "input",
        "description": "Current synthesis down-slope programming; a resistor to GND sets the down-slope rate, and connecting RSYNTH to VREF disables current synthesis."
      },
      {
        "number": "8",
        "name": "CSB",
        "type": "input",
        "description": "Phase-B current sense input, connected to the phase-B current amplifier inverting input through the current synthesis stage during GDB on-time unless RSYNTH is tied to VREF."
      },
      {
        "number": "9",
        "name": "CSA",
        "type": "input",
        "description": "Phase-A current sense input, connected to the phase-A current amplifier inverting input through the current synthesis stage during GDA on-time unless RSYNTH is tied to VREF."
      },
      {
        "number": "10",
        "name": "PKLMT",
        "type": "input",
        "description": "Peak current limit programming; a resistor divider from VREF to this pin sets the cycle-by-cycle peak current limit threshold."
      },
      {
        "number": "11",
        "name": "CAOB",
        "type": "output",
        "description": "Phase-B transconductance current amplifier output to the phase-B PWM comparator inverting input, with current loop compensation connected between this pin and GND."
      },
      {
        "number": "12",
        "name": "CAOA",
        "type": "output",
        "description": "Phase-A transconductance current amplifier output to the phase-A PWM comparator inverting input, with current loop compensation connected between this pin and GND."
      },
      {
        "number": "13",
        "name": "VREF",
        "type": "power_out",
        "description": "6V reference voltage and internal bias, requiring a 0.1µF ceramic bypass capacitor close to this pin and GND."
      },
      {
        "number": "14",
        "name": "GDA",
        "type": "output",
        "description": "Phase-A gate drive, a limited-current output for an external gate-drive device, typically clamped to 13.5V."
      },
      {
        "number": "15",
        "name": "VCC",
        "type": "power_in",
        "description": "Bias voltage input (absolute maximum 22V) requiring a 0.1µF ceramic bypass capacitor close to this pin and GND."
      },
      {
        "number": "16",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground reference for all compensation and programming networks, connected to the system through a separate trace for high-current noise isolation."
      },
      {
        "number": "17",
        "name": "GDB",
        "type": "output",
        "description": "Phase-B gate drive, a limited-current output for an external gate-drive device, typically clamped to 13.5V."
      },
      {
        "number": "18",
        "name": "SS",
        "type": "input",
        "description": "Soft-start and external fault interface; a capacitor to GND sets soft-start with a 10µA source, and pulling below 0.6V immediately disables GDA and GDB."
      },
      {
        "number": "19",
        "name": "RT",
        "type": "input",
        "description": "Timing resistor to GND that sets the internal oscillator running frequency."
      },
      {
        "number": "20",
        "name": "DMAX",
        "type": "input",
        "description": "Maximum duty-cycle programming; a resistor to GND sets the maximum PWM duty cycle based on the ratio RDMX/RRT."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Datasheet lists GND as I/O and VCC/VREF direction by function; types mapped to KiCad classes (GND as"
        ],
        "pages_sent": 9,
        "cost_usd": 0.1155,
        "at": "2026-10-22T18:56:12"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/ucc28070a.pdf",
        "pages": 57,
        "sha256": "632656aea01a2438",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ucc28070apwr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          6.5,
          1.2
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",
        "checked": "2026-10-22",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ucc28070apwr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          6.5,
          1.2
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "7c84d8f10537f17f06f2fb59aea9db0ec633378c994fe1d7c0b76db229cbccba",
        "checked": "2026-10-22",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}