# UC2845ADTR

**Texas Instruments** · AC-DC Controllers And Regulators · SOIC-14

UC2845ADTR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Low-impedance 1 MHz internal error amplifier output that is also the input to the peak current limit/PWM comparator, with open-loop gain (AVOL) of 80 dB; it can sink a maximum of 6 mA and is not internally current limited. |
| 2 | NC | unconnected | No internal connection on the SOIC-14 package. |
| 3 | FB | input | Error amplifier input used to close the power converter voltage feedback loop and tune loop stability. |
| 4 | NC | unconnected | No internal connection on the SOIC-14 package. |
| 5 | ISENSE | input | Input to the peak current limit/PWM comparator; with a current sense resistor it sets the cycle-by-cycle peak current limit, and the maximum peak current sense signal is internally clamped at 1 V. |
| 6 | NC | unconnected | No internal connection on the SOIC-14 package. |
| 7 | RT/CT | input | Internal oscillator timing input programmed with external resistor RT and capacitor CT; TI recommends CT between 470 pF and 4.7 nF and RT between 5 kΩ and 100 kΩ. |
| 8 | PGND | power_in | Power ground and gate driver return path, which can be star-grounded to keep gate driver return current away from the signal ground pin GND and reduce PWM instability. |
| 9 | GND | power_in | Controller signal ground. |
| 10 | OUTPUT | output | 1 A totem-pole gate driver output that can source and sink up to 1 A of gate drive current, and a gate drive resistor must be used to limit that current. |
| 11 | VC | input | Gate driver bias input; the pin must have a bias capacitor at least 10 times the gate capacitance of the main switching FET. |
| 12 | VCC | power_in | Gate driver bias supply input; the pin must have a bias capacitor at least 10 times the gate capacitance of the main switching FET, and the device is specified with VCC of 11 V minimum for operation and a 30 V maximum for low-impedance sources. |
| 13 | NC | unconnected | No internal connection on the SOIC-14 package. |
| 14 | VREF | power_in | PWM controller 5 V reference output that must supply no more than 10 mA in normal operation, is short-circuit protected at about 100 mA, and requires a 1 µF high-frequency bypass capacitor with the VCC capacitor at least 10 times larger than the VREF capacitor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `UC2845ADTR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `uc2845adtr-etched.step` / `uc2845adtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uc2845adtr.step` / `uc2845adtr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](docs/uc2845adtr-datasheet.pdf) (50 pp, sha256 `0eebf00e4b265207`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/uc2845adtr-datasheet.pdf)