component

TX4131L

Public Made by Adom

by adom

XDS DC-DC Converters, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tx4131lfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 16d ago
viewers tx4131l: viewers · Ray 16d ago
package.json Publish 0.1.0 · Ray 16d ago
page.json Set visibility: public · Ray 16d ago
README.md Publish 0.1.0 · Ray 16d ago
tx4131l-etched.glb Publish 0.1.0 · Ray 16d ago
tx4131l-etched.step tx4131l: factory component page (tier=lcsc) · Ray 16d ago
tx4131l-hero.glb tx4131l: hero GLB from the etched model (keeps the MPN mark) · Ray 16d ago
tx4131l-hero.overlay.json Publish 0.1.0 · Ray 16d ago
tx4131l.glb Publish 0.1.0 · Ray 16d ago
tx4131l.kicad_mod Publish 0.1.0 · Ray 16d ago
tx4131l.kicad_sym Publish 0.1.0 · Ray 16d ago
tx4131l.lbr Publish 0.1.0 · Ray 16d ago
tx4131l.step Publish 0.1.0 · Ray 16d ago

TX4131L

XDS · DC-DC Converters · SOP-8

TX4131L from XDS, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRV output Drives the gate of the external MOSFET; the DRV pin voltage is stated as 5.5 V with 30 ns typical rise and fall times at a 1 nF load.
2 VDD power_in Chip supply input; the VDD clamp voltage is 33 V, undervoltage protection turns on at a rising VDD of 6 V and off at a falling VDD of 4 V, and the startup current is 40-100 µA at VDD=5 V.
3 FB1 input Positive input of the output-voltage feedback; FB1 and FB2 are the divider inputs for constant-voltage regulation, with a stated FB1-FB2 difference of 369-391 mV (typically 380 mV) and an absolute limit of -0.3 V to 6 V.
4 FB2 input Negative input of the output-voltage feedback, paired with FB1 to set the constant output voltage; its absolute limit is -0.3 V to 6 V.
5 LDO power_out Internal 5 V LDO output that requires an external capacitor; the datasheet lists the LDO voltage as 5.5 V, and the absolute limit for this pin is -0.3 V to 6 V.
6 VSN input Negative input for inductor current sensing; the VSP-VSN voltage drop is 145-155 mV (typically 150 mV) and the absolute limit is -0.3 V to 6 V.
7 VSS power_in Chip ground pin; the datasheet labels it as chip ground (listed as 'output' in the source text), and it is the reference for the device.
8 VSP input Positive input for inductor current sensing, used with VSN to set the peak current limit; the absolute limit is -0.3 V to 6 V.

Key specifications

Parameter Value
Manufacturer XDS
Package SOP-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD pin maximum voltage VDD 33 V 3
FB1, FB2, LDO, VSP, VSN, DRV maximum voltage VMAX -0.3 6 V 3
ESOP8 package maximum power dissipation PMAX 0.8 W 3
Operating temperature TA -40 85 ℃ 3
Storage temperature TSTG -40 120 ℃ 3
Soldering temperature TSD 240 ℃ 焊接，10秒 3
ESD withstand voltage VESD 2000 V 3
VSN/VSP voltage drop (current sense) VCS 145 150 155 mV 4
FB1, FB2 voltage difference VFB 369 380 391 mV 4
Startup current Istartup 40 100 uA VDD=5V 4
VDD clamp voltage VDD 33 V IVDD<10mA 4
Undervoltage protection turn-on threshold VDD_ON 6 V VDD上升 4
Undervoltage protection turn-off threshold VDD_OFF 4 V VDD下降 4
Operating current IOP 1 mA DRV负载 1nF电容 4
Overcurrent protection threshold VCS_LMT 300 mV 4
Switching frequency Fs 140 KHz 4
DRV pin voltage VDRV 5.5 V 4
DRV rise time TRISE 30 ns DRV脚 1nF电容 4
DRV fall time TFALL 30 ns DRV脚 1nF电容 4
Overtemperature protection threshold OTP_TH 150 ℃ 4
LDO output voltage LDO 5.5 V 4

CAD (KiCad official)

  • Symbol: TX4131L
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tx4131l-etched.step / tx4131l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tx4131l.step / tx4131l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XDS datasheet (8 pp, sha256 6d209f099c99f039, retrieved 2026-10-15, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF