# TSV620AILT

**STMicroelectronics** · Operational Amplifier · SOT-23-6

TSV620AILT from STMicroelectronics, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | In+ | input | Non-inverting input; common mode range extends from (VCC-) - 0.1 V to (VCC+) + 0.1 V. |
| 2 | VCC- | power_in | Negative supply (ground); supply voltage range 1.5 V to 5.5 V between VCC+ and VCC-. |
| 3 | In- | input | Inverting input; input current must be limited to 10 mA by a series resistor. |
| 4 | Out | output | Rail-to-rail amplifier output, within 35 mV max of the rails with a 10 kΩ load, high impedance in shutdown. |
| 5 | SHDN | input | Active-low shutdown: high enables the amplifier, pulled to VCC- disables it, and it must never be left floating. |
| 6 | VCC+ | power_in | Positive supply, 1.5 V to 5.5 V operating range, with 6 V absolute maximum; 10 nF decoupling is advised close to the pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOT-23-6 |
| Category | Amplifiers/Comparators |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage (25 °C, 1.8 V) | Vio |  |  | 0.8 | mV | VCC+ = 1.8 V, Top = 25 °C | 4 |
| Input offset current (25 °C, 1.8 V) | Iio |  | 1 | 10 | pA | VCC+ = 1.8 V, Vout = VCC/2 | 4 |
| Input bias current (25 °C, 1.8 V) | Iib |  | 1 | 10 | pA | VCC+ = 1.8 V, Vout = VCC/2 | 4 |
| Common mode rejection ratio (1.8 V) | CMR | 53 | 74 |  | dB | VCC+ = 1.8 V, 0 V to 1.8 V, Vout = 0.9 V | 4 |
| Large signal voltage gain (1.8 V) | Avd | 78 | 95 |  | dB | VCC+ = 1.8 V, RL = 10 kΩ, Vout = 0.5 V to 1.3 V | 4 |
| High level output voltage (1.8 V) | VOH |  | 5 | 35 | mV | VCC+ = 1.8 V, RL = 10 kΩ, VOH = VCC - Vout | 4 |
| Low level output voltage (1.8 V) | VOL |  | 4 | 35 | mV | VCC+ = 1.8 V, RL = 10 kΩ | 4 |
| Output sink current (1.8 V) | Isink |  | 6 | 12 | mA | VCC+ = 1.8 V, Vo = 1.8 V | 4 |
| Output source current (1.8 V) | Isource |  | 6 | 10 | mA | VCC+ = 1.8 V, Vo = 0 V | 4 |
| Supply current per operator (1.8 V) | ICC |  | 25 | 31 | µA | VCC+ = 1.8 V, No load, Vout = VCC/2 | 4 |
| Gain bandwidth product (1.8 V) | GBP | 275 | 340 |  | kHz | VCC+ = 1.8 V, RL = 10 kΩ, CL = 100 pF, f = 100 kHz | 4 |
| Phase margin (1.8 V) | φm | 45 |  |  | Degrees | VCC+ = 1.8 V, RL = 10 kΩ, CL = 100 pF | 4 |
| Gain margin (1.8 V) | Gm | 9 |  |  | dB | VCC+ = 1.8 V, RL = 10 kΩ, CL = 100 pF | 4 |
| Slew rate (1.8 V) | SR | 0.084 | 0.11 | 0.14 | V/µs | VCC+ = 1.8 V, RL = 10 kΩ, CL = 100 pF, Av = 1 | 4 |
| Input offset voltage (25 °C, 3.3 V) | Vio |  |  | 0.8 | mV | VCC+ = 3.3 V, Top = 25 °C | 6 |
| Input offset current (25 °C, 3.3 V) | Iio |  | 1 | 10 | pA | VCC+ = 3.3 V, Vicm = VCC/2 | 6 |
| Input bias current (25 °C, 3.3 V) | Iib |  | 1 | 10 | pA | VCC+ = 3.3 V, Vicm = VCC/2 | 6 |
| Common mode rejection ratio (3.3 V) | CMR | 57 | 79 |  | dB | VCC+ = 3.3 V, 0 V to 3.3 V, Vout = 1.75 V | 6 |
| Large signal voltage gain (3.3 V) | Avd | 81 | 98 |  | dB | VCC+ = 3.3 V, RL = 10 kΩ, Vout = 0.5 V to 2.8 V | 6 |
| High level output voltage (3.3 V) | VOH |  | 5 | 35 | mV | VCC+ = 3.3 V, RL = 10 kΩ, VOH = VCC - Vout | 6 |
| Low level output voltage (3.3 V) | VOL |  | 4 | 35 | mV | VCC+ = 3.3 V, RL = 10 kΩ | 6 |
| Output sink current (3.3 V) | Isink |  | 30 | 45 | mA | VCC+ = 3.3 V, Vo = 5 V | 6 |
| Output source current (3.3 V) | Isource |  | 30 | 38 | mA | VCC+ = 3.3 V, Vo = 0 V | 6 |
| Supply current per operator (3.3 V) | ICC |  | 26 | 33 | µA | VCC+ = 3.3 V, No load, Vout = 2.5 V | 6 |
| Gain bandwidth product (3.3 V) | GBP | 310 | 380 |  | kHz | VCC+ = 3.3 V, RL = 10 kΩ, CL = 100 pF, f = 100 kHz | 6 |
| Phase margin (3.3 V) | φm | 45 |  |  | Degrees | VCC+ = 3.3 V, RL = 10 kΩ, CL = 100 pF | 6 |
| Gain margin (3.3 V) | Gm | 9 |  |  | dB | VCC+ = 3.3 V, RL = 10 kΩ, CL = 100 pF | 6 |
| Slew rate (3.3 V) | SR | 0.094 | 0.12 |  | V/µs | VCC+ = 3.3 V, RL = 10 kΩ, CL = 100 pF, AV = 1 | 6 |
| Input offset voltage (25 °C, 5 V) | Vio |  |  | 0.8 | mV | VCC+ = 5 V, Top = 25 °C | 7 |
| Input offset current (25 °C, 5 V) | Iio |  | 1 | 10 | pA | VCC+ = 5 V, Vicm = VCC/2 | 7 |
| Input bias current (25 °C, 5 V) | Iib |  | 1 | 10 | pA | VCC+ = 5 V, Vicm = VCC/2 | 7 |
| Common mode rejection ratio (5 V) | CMR | 60 | 80 |  | dB | VCC+ = 5 V, 0 V to 5 V, Vout = 2.5 V | 7 |
| Supply voltage rejection ratio (5 V) | SVR | 75 | 102 |  | dB | VCC = 1.8 to 5 V | 7 |
| Large signal voltage gain (5 V) | Avd | 85 | 98 |  | dB | VCC+ = 5 V, RL = 10 kΩ, Vout = 0.5 V to 4.5 V | 7 |
| High level output voltage (5 V) | VOH |  | 7 | 35 | mV | VCC+ = 5 V, RL = 10 kΩ, VOH = VCC - Vout | 7 |
| Low level output voltage (5 V) | VOL |  | 6 | 35 | mV | VCC+ = 5 V, RL = 10 kΩ | 7 |
| Output sink current (5 V) | Isink |  | 40 | 69 | mA | VCC+ = 5 V, Vo = 5 V | 7 |
| Output source current (5 V) | Isource |  | 40 | 74 | mA | VCC+ = 5 V, Vo = 0 V | 7 |
| Supply current per operator (5 V) | ICC |  | 29 | 36 | µA | VCC+ = 5 V, No load, Vout = 2.5 V | 7 |
| Gain bandwidth product (5 V) | GBP | 350 | 420 |  | kHz | VCC+ = 5 V, RL = 10 kΩ, CL = 100 pF, f = 100 kHz | 7 |
| Phase margin (5 V) | φm | 45 |  |  | Degrees | VCC+ = 5 V, RL = 10 kΩ, CL = 100 pF | 7 |
| Gain margin (5 V) | Gm | 9 |  |  | dB | VCC+ = 5 V, RL = 10 kΩ, CL = 100 pF | 7 |
| Slew rate (5 V) | SR | 0.108 | 0.14 |  | V/µs | VCC+ = 5 V, RL = 10 kΩ, CL = 100 pF, AV = 1 | 7 |
| Supply current in shutdown mode (all operators, 5 V) | ICC |  | 5 | 50 | nA | VCC = 5 V, SHDN = VCC- | 8 |
| Amplifier turn-on time (5 V) | ton |  |  | 300 | ns | VCC = 5 V, RL = 2 kΩ, Vout = (VCC-) to (VCC-) + 0.2 | 8 |
| Amplifier turn-off time (5 V) | toff |  |  | 30 | ns | VCC = 5 V, RL = 2 kΩ, Vout = (VCC+) - 0.5 to (VCC+) + 0.7 | 8 |
| SHDN logic high (5 V) | VIH | 4.5 |  |  | V | VCC = 5 V | 8 |
| SHDN logic low (5 V) | VIL |  |  | 0.5 | V | VCC = 5 V | 8 |
| Output leakage in shutdown mode (5 V) | IOLeak |  |  | 50 | nA | VCC = 5 V, SHDN = VCC- | 8 |
| Supply voltage | VCC | 1.5 |  | 5.5 | V |  | 3 |
| Operating free air temperature range | Toper | -40 |  | 125 | °C |  | 3 |
| Supply voltage (absolute maximum) | VCC |  |  | 6 | V |  | 3 |
| Input current | Iin |  |  | 10 | mA | Must be limited by series input resistor | 3 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| Maximum junction temperature | Tj |  |  | 150 | °C |  | 3 |
| ESD HBM |  |  |  | 4 | kV | Human body model | 3 |
| ESD machine model |  |  |  | 300 | V | Machine model | 3 |
| ESD charged device model |  |  |  | 1.5 | kV | Charged device model | 3 |
| Thermal resistance junction to ambient (SOT23-6) | Rthja |  | 240 |  | °C/W | SOT23-6, typical value | 3 |

## CAD (KiCad official)

- Symbol: `TSV620AILT`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `tsv620ailt-etched.step` / `tsv620ailt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tsv620ailt.step` / `tsv620ailt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589837931016708096) (24 pp, sha256 `e2cbf1a22b9fb858`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tsv620ailt-datasheet.pdf)