component

TPW4053-SR

Public Made by Adom

by adom

3PEAK Analog Switches / Multiplexers, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentcomm-uarttpw4053-sr
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs tpw4053-sr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json tpw4053-sr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1d ago
README.md tpw4053-sr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
tpw4053-sr-etched.fit.json tpw4053-sr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tpw4053-sr-etched.glb tpw4053-sr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tpw4053-sr-etched.step tpw4053-sr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tpw4053-sr.glb Publish 0.1.0 · Ray 1mo ago
tpw4053-sr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tpw4053-sr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tpw4053-sr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 16 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
tpw4053-sr.step Publish 0.1.0 · Ray 1mo ago

TPW4053-SR

3PEAK · Analog Switches / Multiplexers · SOIC-16

TPW4053-SR from 3PEAK, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B1 bidirectional Channel B1 analog switch throw. Connects to common B (pin 15) when the B-channel select routes to the '1' side. Signal range VEE to VCC; ±25 mA max switch current.
2 B0 bidirectional Channel B0 analog switch throw. Connects to common B (pin 15) when the B-channel select routes to the '0' side. Signal range VEE to VCC; ±25 mA max switch current.
3 C1 bidirectional Channel C1 analog switch throw. Connects to common C (pin 4) when the C-channel select routes to the '1' side. Signal range VEE to VCC; ±25 mA max switch current.
4 C bidirectional C common analog input/output. Routed to either C0 (pin 5) or C1 (pin 3) depending on the S2 select input and enable. Bidirectional analog signal path.
5 C0 bidirectional Channel C0 analog switch throw. Connects to common C (pin 4) when the C-channel select routes to the '0' side. Signal range VEE to VCC; ±25 mA max switch current.
6 /E input Active-low enable input. When /E is LOW the selected switches are enabled per the S0/S1/S2 truth table; when /E is HIGH all three switches are turned off. Digital input, VIH = 2.0 V min (2.4 V at 9-11 V VCC), VIL = 0.8 V max. Must be held HIGH or LOW; do not float.
7 VEE power_in Negative analog supply. Ground for single-supply operation (VEE = 0 V) or negative rail for dual-supply operation (VEE down to −5.5 V). Sets the lower analog signal limit; abs-max −6.5 V to 0.5 V vs GND.
8 GND power_in Digital ground reference. VCC − GND recommended 3 V to 12 V; VEE − GND recommended −6 V to 0 V.
9 S2 input Select input for the C channel (selects C0 vs C1). Digital CMOS input, VIH = 2.0 V min (2.4 V at 9-11 V VCC), VIL = 0.8 V max; input leakage ±1 µA max. Must be driven HIGH or LOW, not floated.
10 S1 input Select input for the B channel (selects B0 vs B1). Digital CMOS input, VIH = 2.0 V min (2.4 V at 9-11 V VCC), VIL = 0.8 V max; input leakage ±1 µA max. Must be driven HIGH or LOW, not floated.
11 S0 input Select input for the A channel (selects A0 vs A1). Digital CMOS input, VIH = 2.0 V min (2.4 V at 9-11 V VCC), VIL = 0.8 V max; input leakage ±1 µA max. Must be driven HIGH or LOW, not floated.
12 A0 bidirectional Channel A0 analog switch throw. Connects to common A (pin 14) when the A-channel select routes to the '0' side. Signal range VEE to VCC; ±25 mA max switch current.
13 A1 bidirectional Channel A1 analog switch throw. Connects to common A (pin 14) when the A-channel select routes to the '1' side. Signal range VEE to VCC; ±25 mA max switch current.
14 A bidirectional A common analog input/output. Routed to either A0 (pin 12) or A1 (pin 13) depending on the S0 select input and enable. Bidirectional analog signal path.
15 B bidirectional B common analog input/output. Routed to either B0 (pin 2) or B1 (pin 1) depending on the S1 select input and enable. Bidirectional analog signal path.
16 VCC power_in Positive supply. Single-supply 3 V to 12 V above GND, or dual-supply 4.5-5.5 V above GND with VEE at −4.5 to −5.5 V. Sets the upper analog signal limit; abs-max −0.5 V to 13 V vs GND. ICC quiescent 4-16 µA typ over the supply range.

Key specifications

Parameter Value
Manufacturer 3PEAK
Package SOIC-16
Category Comm/UART
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • TPW4053-SR
  • TPW4053-SRTR
  • TPW4053-SR-TR

CAD (KiCad official)

  • Symbol: TPW4053-SR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: tpw4053-sr-etched.step / tpw4053-sr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpw4053-sr.step / tpw4053-sr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tpw4053-sr.step 217 KB You want the bare part, or you mark your own boards.
tpw4053-sr-etched.step 2.5 MB You want the part with TPW4053-SR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 634 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: 3PEAK datasheet (15 pp, sha256 cdb913c6bba9a54e, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF