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TPS7B4253QDDARQ1

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs tps7b4253qddarq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
viewers tps7b4253qddarq1: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md tps7b4253qddarq1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 17d ago
tps7b4253qddarq1-etched.fit.json tps7b4253qddarq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
tps7b4253qddarq1-etched.glb tps7b4253qddarq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
tps7b4253qddarq1-etched.step tps7b4253qddarq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
tps7b4253qddarq1.glb Publish 0.1.0 · Ray 1mo ago
tps7b4253qddarq1.kicad_mod Publish 0.1.0 · Ray 1mo ago
tps7b4253qddarq1.kicad_sym Publish 0.1.0 · Ray 1mo ago
tps7b4253qddarq1.lbr Publish 0.1.0 · Ray 1mo ago
tps7b4253qddarq1.step Publish 0.1.0 · Ray 1mo ago

TPS7B4253QDDARQ1

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP

TPS7B4253QDDARQ1 from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output. Block to GND with a ceramic capacitor (10 to 500 µF, ESR 1 mΩ to 20 Ω) close to the device pins per the Output Capacitor requirements. Supplies up to 300 mA at 2 V to 40 V (SO PowerPAD).
2 NC unconnected No internal connection.
3 GND power_in Ground reference.
4 FB input Feedback input for the tracker. Connects to an external resistor divider (or directly to OUT) to set the output voltage. Rated -1 V to 45 V absolute maximum; recommended 2 V to 18 V (SO PowerPAD).
5 ADJ input Reference / adjust input. Also serves as the enable in this package: a low signal (<0.7 V) disables the device, a high signal (≥2 V, SO PowerPAD) enables it. The reference voltage can be applied directly or through a divider; add a decoupling capacitor close to the pin. Recommended range 2 V to 18 V.
6 GND power_in Ground reference (second GND pin, tied to pin 3 internally).
7 NC unconnected No internal connection.
8 IN power_in Unregulated supply input. Recommended 4 V to 40 V (absolute max −40 V to 45 V, supports 45-V load dump and reverse polarity). Connect a bypass capacitor close to the pin to compensate for line influences.
9 PAD passive Exposed thermal pad. Connect to the GND pin/plane for best thermal performance, or leave floating (per the datasheet, connect to GND or leave floating).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8-EP
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • TPS7B4253QDDARQ1
  • TPS7B4253QDDARQ1PWPR
  • TPS7B4253QDDARQ1PWPRQ1

CAD (KiCad official)

  • Symbol: TPS7B4253QDDARQ1
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: tps7b4253qddarq1-etched.step / tps7b4253qddarq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7b4253qddarq1.step / tps7b4253qddarq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 99574acc751879ee, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF