component
TPS75005RGWR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304
{
"schema_version": 1,
"type": "component",
"slug": "tps75005rgwr",
"title": "TPS75005RGWR",
"brief": "Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"embedded processors & controllers",
"tps75005rgwr",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "TPS75005RGWR",
"manufacturer": "Texas Instruments",
"package": "VQFN-20-EP(5x5)",
"pin_count": 21,
"category": "Embedded Processors & Controllers",
"subcategory": "Microcontrollers (MCU/MPU/SOC)",
"datasheet": "https://www.ti.com/cn/lit/gpn/tps75005",
"parts": {
"symbol": "tps75005rgwr.kicad_sym",
"footprint": "tps75005rgwr.kicad_mod",
"model_3d": "tps75005rgwr-hero.glb",
"model_3d_plain": "tps75005rgwr.glb",
"model_3d_step": "tps75005rgwr-etched.step",
"model_3d_step_plain": "tps75005rgwr.step",
"lbr": "tps75005rgwr.lbr"
},
"distributor_links": {
"lcsc": "C2841532",
"digikey": "296-29880-2-ND",
"mouser": "595-TPS75005RGWR"
},
"distributor_check": {
"checked_at": "2026-10-08T23:11:50Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "296-29880-2-ND",
"status": "found",
"lifecycle": "Not For New Designs"
},
"mouser": {
"pn": "595-TPS75005RGWR",
"status": "found",
"lifecycle": "Not Recommended for New Designs"
}
},
"pins": [
{
"number": "1",
"name": "OUT2",
"type": "power_out",
"description": "LDO2 (3.3 V) regulator output; connect a 10-µF X5R or X7R capacitor between this pin and ground close to the device."
},
{
"number": "2",
"name": "OUT2_S",
"type": "input",
"description": "LDO2 output voltage sense input; connect directly to the output capacitor close to pin 1."
},
{
"number": "3",
"name": "CT2",
"type": "passive",
"description": "SVS2 internal power-good delay setting; leave open for the default delay or connect a capacitor CT2 between this pin and GND to program the delay, and do not connect a regular oscilloscope probe for monitoring."
},
{
"number": "4",
"name": "SS2",
"type": "passive",
"description": "LDO2 soft-start setting; leave open for the default ramp-up or connect a capacitor between this pin and GND to program the VOUT2 ramp-up slew rate, and do not connect a regular oscilloscope probe for monitoring."
},
{
"number": "5",
"name": "VDET",
"type": "output",
"description": "Output of SVS3 (open-drain) that requires a pull-up resistor, typically 100 kΩ to IN; it outputs logic-H when VMON > VSVS3 and logic-L when VMON < VSVS3."
},
{
"number": "6",
"name": "GND",
"type": "power_in",
"description": "Ground; tie to the thermal pad and maximize the copper in this area for optimal performance."
},
{
"number": "7",
"name": "GND",
"type": "power_in",
"description": "Ground; tie to the thermal pad and maximize the copper in this area for optimal performance."
},
{
"number": "8",
"name": "SEQ",
"type": "input",
"description": "Sequence select: logic-L powers up LDO1 first and then LDO2 (powering down LDO2 first), logic-H powers up LDO2 first and then LDO1; SEQ should be hard-wired to IN or GND."
},
{
"number": "9",
"name": "VSET",
"type": "input",
"description": "LDO1 output voltage setting; logic-H sets VOUT1 to 1.9 V and logic-L sets VOUT1 to 1.8 V, and it is recommended to tie this pin to IN or GND."
},
{
"number": "10",
"name": "PG",
"type": "output",
"description": "Power-good output (open-drain) that requires a pull-up resistor, typically 100 kΩ to OUT2; it outputs logic-H when VOUT1 > VSVS1 and VOUT2 > VSVS2."
},
{
"number": "11",
"name": "TEST",
"type": "unconnected",
"description": "Test pin for test and debugging purposes only; do not connect this pin."
},
{
"number": "12",
"name": "SS1",
"type": "passive",
"description": "LDO1 soft-start setting; leave open for the default ramp-up or connect a capacitor of 10 nF or less between this pin and GND to program the VOUT1 ramp-up slew rate, and do not connect a regular oscilloscope probe for monitoring."
},
{
"number": "13",
"name": "CT1",
"type": "passive",
"description": "SVS1 internal power-good delay setting; leave open for the default delay or connect capacitor CT1 between this node and GND to program the delay, and do not connect a regular oscilloscope probe for monitoring."
},
{
"number": "14",
"name": "OUT1_S",
"type": "input",
"description": "LDO1 output voltage sense input; connect directly to the output capacitor close to pin 15."
},
{
"number": "15",
"name": "OUT1",
"type": "power_out",
"description": "LDO1 (1.8 V/1.9 V) regulator output; connect a 10-µF X5R or X7R capacitor between this pin and ground close to the device."
},
{
"number": "16",
"name": "VMON",
"type": "input",
"description": "Monitor input of the third voltage detector; a resistor divider between the monitored rail and GND sets the threshold, which is 1.206 V."
},
{
"number": "17",
"name": "EN",
"type": "input",
"description": "Enable input; logic-H triggers the power-up sequence and logic-L triggers the power-down sequence, and the sequencing logic prevents power-up until the output rails are pulled to GND."
},
{
"number": "18",
"name": "IN",
"type": "power_in",
"description": "Power supply input to the device; connect a 10-µF X5R or X7R dielectric capacitor between IN and GND close to the device."
},
{
"number": "19",
"name": "IN",
"type": "power_in",
"description": "Power supply input to the device; connect a 10-µF X5R or X7R dielectric capacitor between IN and GND close to the device."
},
{
"number": "20",
"name": "NC",
"type": "unconnected",
"description": "Not internally connected; this pin can be tied to either IN or GND to simplify layout."
},
{
"number": "21",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The thermal pad is described on page 6 ('Pad for thermal dissipation... Tie this pin to GND') but ha; The datasheet gives no KiCad-style type for TEST; it says only 'Do not connect this pin', so 'unconn; The pin-description text for CT2 (pin 3) and CT1 (pin 13) is garbled in the extracted text, so the p",
"exposed pad 21 added from the footprint"
],
"pages_sent": 8,
"cost_usd": 0.0728,
"at": "2026-10-08T23:10:51"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/tps75005",
"pages": 33,
"sha256": "30c5c221a47ec3b7",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 21,
"described": 21,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "tps75005rgwr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5,
5,
0.77
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "9466f19e7a94c1920e0c82ac10746517bca0b846bd3c01a7053914bd9856799f",
"checked": "2026-10-08",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "tps75005rgwr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5,
5,
0.77
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "39ead543acf98f8da972ae9422bc35e6a2c9ad8b02e60c2830f875667b12c11a",
"checked": "2026-10-08",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "VQFN-20-EP(5x5)",
"Category": "Embedded Processors & Controllers",
"Pins": "21"
}
},
"variants": [],
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"tps75005rgwr"
],
"discovery_pitch": "TPS75005RGWR (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"tps75005rgwr.kicad_sym",
"tps75005rgwr.kicad_mod",
"tps75005rgwr.glb",
"tps75005rgwr.step",
"tps75005rgwr.lbr",
"docs/hero.png",
"docs/tps75005rgwr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"tps75005rgwr-hero.glb",
"tps75005rgwr-hero.overlay.json"
],
"visibility": {
"public": true
}
}