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TPS75005RGWR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS75005RGWR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-20-EP(5x5)

TPS75005RGWR from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT2 power_out LDO2 (3.3 V) regulator output; connect a 10-µF X5R or X7R capacitor between this pin and ground close to the device.
2 OUT2_S input LDO2 output voltage sense input; connect directly to the output capacitor close to pin 1.
3 CT2 passive SVS2 internal power-good delay setting; leave open for the default delay or connect a capacitor CT2 between this pin and GND to program the delay, and do not connect a regular oscilloscope probe for monitoring.
4 SS2 passive LDO2 soft-start setting; leave open for the default ramp-up or connect a capacitor between this pin and GND to program the VOUT2 ramp-up slew rate, and do not connect a regular oscilloscope probe for monitoring.
5 VDET output Output of SVS3 (open-drain) that requires a pull-up resistor, typically 100 kΩ to IN; it outputs logic-H when VMON > VSVS3 and logic-L when VMON < VSVS3.
6 GND power_in Ground; tie to the thermal pad and maximize the copper in this area for optimal performance.
7 GND power_in Ground; tie to the thermal pad and maximize the copper in this area for optimal performance.
8 SEQ input Sequence select: logic-L powers up LDO1 first and then LDO2 (powering down LDO2 first), logic-H powers up LDO2 first and then LDO1; SEQ should be hard-wired to IN or GND.
9 VSET input LDO1 output voltage setting; logic-H sets VOUT1 to 1.9 V and logic-L sets VOUT1 to 1.8 V, and it is recommended to tie this pin to IN or GND.
10 PG output Power-good output (open-drain) that requires a pull-up resistor, typically 100 kΩ to OUT2; it outputs logic-H when VOUT1 > VSVS1 and VOUT2 > VSVS2.
11 TEST unconnected Test pin for test and debugging purposes only; do not connect this pin.
12 SS1 passive LDO1 soft-start setting; leave open for the default ramp-up or connect a capacitor of 10 nF or less between this pin and GND to program the VOUT1 ramp-up slew rate, and do not connect a regular oscilloscope probe for monitoring.
13 CT1 passive SVS1 internal power-good delay setting; leave open for the default delay or connect capacitor CT1 between this node and GND to program the delay, and do not connect a regular oscilloscope probe for monitoring.
14 OUT1_S input LDO1 output voltage sense input; connect directly to the output capacitor close to pin 15.
15 OUT1 power_out LDO1 (1.8 V/1.9 V) regulator output; connect a 10-µF X5R or X7R capacitor between this pin and ground close to the device.
16 VMON input Monitor input of the third voltage detector; a resistor divider between the monitored rail and GND sets the threshold, which is 1.206 V.
17 EN input Enable input; logic-H triggers the power-up sequence and logic-L triggers the power-down sequence, and the sequencing logic prevents power-up until the output rails are pulled to GND.
18 IN power_in Power supply input to the device; connect a 10-µF X5R or X7R dielectric capacitor between IN and GND close to the device.
19 IN power_in Power supply input to the device; connect a 10-µF X5R or X7R dielectric capacitor between IN and GND close to the device.
20 NC unconnected Not internally connected; this pin can be tied to either IN or GND to simplify layout.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-20-EP(5x5)
Category Embedded Processors & Controllers
Pins 21

CAD (KiCad official)

  • Symbol: TPS75005RGWR
  • Footprint: Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm
  • 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps75005rgwr-etched.step / tps75005rgwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps75005rgwr.step / tps75005rgwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 30c5c221a47ec3b7, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF