# TPS65400RGZT

**Texas Instruments** · DC-DC Converters · VQFN-48-EP(7x7)

TPS65400RGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CB1 | passive | Bootstrap pin for the SW1 high-side MOSFET gate drive; CB1 is referenced to SW1 with a maximum of 7.0 V in recommended operating conditions. |
| 2 | SW1 | power_out | Switch pin for SW1; SW1 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |
| 3 | SW1 | power_out | Switch pin for SW1; SW1 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |
| 4 | SW1 | power_out | Switch pin for SW1; SW1 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |
| 5 | PVIN1 | power_in | Power input for the SW1 buck switching regulator, rated 4.5 V to 18 V. |
| 6 | PVIN2 | power_in | Power input for the SW2 buck switching regulator, rated 4.5 V to 18 V. |
| 7 | PGND1 | power_in | Power ground for the buck converters. |
| 8 | PGND2 | power_in | Power ground for the buck converters. |
| 9 | SW2 | power_out | Switch pin for SW2; SW2 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |
| 10 | SW2 | power_out | Switch pin for SW2; SW2 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |
| 11 | SW2 | power_out | Switch pin for SW2; SW2 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |
| 12 | CB2 | passive | Bootstrap pin for the SW2 high-side MOSFET gate drive; CB2 is referenced to SW2 with a maximum of 7.0 V in recommended operating conditions. |
| 13 | ENSW2 | input | Active-high enable input for SW2 with a 2-µA internal pullup; recommended maximum is 3.3 V. |
| 14 | VFB2 | input | Feedback input for SW2; the recommended range is 0.6 V to 1.87 V. |
| 15 | COMP2 | passive | Compensation pin for the SW2 external compensation network; pulling this pin high to VDDA configures the SW1 controller to control both SW1 and SW2. |
| 16 | SS2/PG2 | bidirectional | Soft-start pin for SW2 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD2 signal. |
| 17 | PGOOD | output | Global power-good output that is by default the logical AND of all switcher PGOOD signals, and goes low if all switchers are disabled. |
| 18 | VDDG | power_out | Supply for the gate drives, to be bypassed locally to PGND; recommended range is -0.3 V to 7.0 V. |
| 19 | VDDA | power_out | Output of the internal regulator for analog controls; recommended range is -0.3 V to 7.0 V. |
| 20 | VDDD | power_out | 3.3-V output of the internal regulator for digital controls; recommended range is -0.3 V to 3.3 V. |
| 21 | AGND | power_in | Ground connection for analog controls. |
| 22 | VIN | power_in | Analog VIN power input for the VDDD, VDDA, and VGATE subregulators; recommended range is -0.3 V to 18.0 V. |
| 23 | CE | input | Chip enable with an internal pullup that defaults high when floating; pull low with an open-drain output to disable, since push-pull drive is not recommended, and recommended range is -0.3 V to 7.0 V. |
| 24 | SS3/PG3 | bidirectional | Soft-start pin for SW3 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD3 signal. |
| 25 | COMP3 | passive | Compensation pin for the SW3 external compensation network; recommended range is -0.3 V to 7.0 V. |
| 26 | VFB3 | input | Feedback input for SW3; the recommended range is 0.6 V to 1.87 V. |
| 27 | ENSW3 | input | Active-high enable input for SW3 with a 2-µA internal pullup; recommended maximum is 3.3 V. |
| 28 | CB3 | passive | Bootstrap pin for the SW3 high-side MOSFET gate drive; CB3 is referenced to SW3 with a maximum of 7.0 V in recommended operating conditions. |
| 29 | SW3 | power_out | Switch pin for SW3; the maximum rated output current is 2 A and the pin is rated -1.0 V to 18.0 V. |
| 30 | PVIN3 | power_in | Power input for the SW3 buck switching regulator, rated 4.5 V to 18 V. |
| 31 | PVIN4 | power_in | Power input for the SW4 buck switching regulator, rated 4.5 V to 18 V. |
| 32 | SW4 | power_out | Switch pin for SW4; the maximum rated output current is 2 A and the pin is rated -1.0 V to 18.0 V. |
| 33 | CB4 | passive | Bootstrap pin for the SW4 high-side MOSFET gate drive; CB4 is referenced to SW4 with a maximum of 7.0 V in recommended operating conditions. |
| 34 | ENSW4 | input | Active-high enable input for SW4 with a 2-µA internal pullup; recommended maximum is 3.3 V. |
| 35 | VFB4 | input | Feedback input for SW4; the recommended range is 0.6 V to 1.87 V. |
| 36 | COMP4 | passive | Compensation pin for the SW4 external compensation network; pulling this pin high to VDDA configures the SW3 controller to control both SW3 and SW4. |
| 37 | SS4/PG4 | bidirectional | Soft-start pin for SW4 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD4 signal. |
| 38 | I2CADDR | input | Selects the 7-bit I2C address through a resistor to AGND, sampled only at startup during tRESET_DELAY after the rising edge of CE or RST_N; tying it directly to VDDD is recommended if I2C is not used. |
| 39 | RST_N | input | Digital logic reset; when low, all switchers are disabled, and configuration is reloaded from EEPROM when it is deasserted; recommended range is -0.3 V to 3.3 V. |
| 40 | RCLOCK_SYNC | passive | Resistor input that sets the primary clock frequency from 275 kHz to 2.2 MHz, or serves as the clock sync input; recommended range is -0.3 V to 3.3 V. |
| 41 | I2CALERT | output | Open-drain output pulled low for 200 µs when an I2C watchdog timeout is detected on SDA or SCL; recommended range is -0.3 V to 3.3 V. |
| 42 | SDA | bidirectional | Data input/output pin for the I2C bus; recommended range is -0.3 V to 3.3 V. |
| 43 | SCL | input | Clock input pin for the I2C bus; recommended range is -0.3 V to 3.3 V. |
| 44 | CLK_OUT | output | Clock output, open-collector, which requires a pull-up; recommended range is -0.3 V to 3.3 V. |
| 45 | SS1/PG1 | bidirectional | Soft-start pin for SW1 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD1 signal. |
| 46 | COMP1 | passive | Compensation pin for the SW1 external compensation network; recommended range is -0.3 V to 7.0 V. |
| 47 | VFB1 | input | Feedback input for SW1; the recommended range is 0.6 V to 1.87 V. |
| 48 | ENSW1/ENSEQ | input | Active-high enable input for SW1 (also the sequence start/stop pin in single-enable mode) with a 2-µA internal pullup; recommended maximum is 3.3 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Power Management (PMIC) |
| Pins | 49 |

## CAD (KiCad official)

- Symbol: `TPS65400RGZT`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `tps65400rgzt-etched.step` / `tps65400rgzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps65400rgzt.step` / `tps65400rgzt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps65400) (80 pp, sha256 `f5ff79cbf2573561`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps65400rgzt-datasheet.pdf)