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TPS65400RGZT
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Texas Instruments DC-DC Converters, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# TPS65400RGZT++**Texas Instruments** · DC-DC Converters · VQFN-48-EP(7x7)++TPS65400RGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CB1 | passive | Bootstrap pin for the SW1 high-side MOSFET gate drive; CB1 is referenced to SW1 with a maximum of 7.0 V in recommended operating conditions. |+| 2 | SW1 | power_out | Switch pin for SW1; SW1 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |+| 3 | SW1 | power_out | Switch pin for SW1; SW1 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |+| 4 | SW1 | power_out | Switch pin for SW1; SW1 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |+| 5 | PVIN1 | power_in | Power input for the SW1 buck switching regulator, rated 4.5 V to 18 V. |+| 6 | PVIN2 | power_in | Power input for the SW2 buck switching regulator, rated 4.5 V to 18 V. |+| 7 | PGND1 | power_in | Power ground for the buck converters. |+| 8 | PGND2 | power_in | Power ground for the buck converters. |+| 9 | SW2 | power_out | Switch pin for SW2; SW2 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |+| 10 | SW2 | power_out | Switch pin for SW2; SW2 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |+| 11 | SW2 | power_out | Switch pin for SW2; SW2 is rated for -1.0 V to 18.0 V and supplies up to 4 A. |+| 12 | CB2 | passive | Bootstrap pin for the SW2 high-side MOSFET gate drive; CB2 is referenced to SW2 with a maximum of 7.0 V in recommended operating conditions. |+| 13 | ENSW2 | input | Active-high enable input for SW2 with a 2-µA internal pullup; recommended maximum is 3.3 V. |+| 14 | VFB2 | input | Feedback input for SW2; the recommended range is 0.6 V to 1.87 V. |+| 15 | COMP2 | passive | Compensation pin for the SW2 external compensation network; pulling this pin high to VDDA configures the SW1 controller to control both SW1 and SW2. |+| 16 | SS2/PG2 | bidirectional | Soft-start pin for SW2 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD2 signal. |+| 17 | PGOOD | output | Global power-good output that is by default the logical AND of all switcher PGOOD signals, and goes low if all switchers are disabled. |+| 18 | VDDG | power_out | Supply for the gate drives, to be bypassed locally to PGND; recommended range is -0.3 V to 7.0 V. |+| 19 | VDDA | power_out | Output of the internal regulator for analog controls; recommended range is -0.3 V to 7.0 V. |+| 20 | VDDD | power_out | 3.3-V output of the internal regulator for digital controls; recommended range is -0.3 V to 3.3 V. |+| 21 | AGND | power_in | Ground connection for analog controls. |+| 22 | VIN | power_in | Analog VIN power input for the VDDD, VDDA, and VGATE subregulators; recommended range is -0.3 V to 18.0 V. |+| 23 | CE | input | Chip enable with an internal pullup that defaults high when floating; pull low with an open-drain output to disable, since push-pull drive is not recommended, and recommended range is -0.3 V to 7.0 V. |+| 24 | SS3/PG3 | bidirectional | Soft-start pin for SW3 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD3 signal. |+| 25 | COMP3 | passive | Compensation pin for the SW3 external compensation network; recommended range is -0.3 V to 7.0 V. |+| 26 | VFB3 | input | Feedback input for SW3; the recommended range is 0.6 V to 1.87 V. |+| 27 | ENSW3 | input | Active-high enable input for SW3 with a 2-µA internal pullup; recommended maximum is 3.3 V. |+| 28 | CB3 | passive | Bootstrap pin for the SW3 high-side MOSFET gate drive; CB3 is referenced to SW3 with a maximum of 7.0 V in recommended operating conditions. |+| 29 | SW3 | power_out | Switch pin for SW3; the maximum rated output current is 2 A and the pin is rated -1.0 V to 18.0 V. |+| 30 | PVIN3 | power_in | Power input for the SW3 buck switching regulator, rated 4.5 V to 18 V. |+| 31 | PVIN4 | power_in | Power input for the SW4 buck switching regulator, rated 4.5 V to 18 V. |+| 32 | SW4 | power_out | Switch pin for SW4; the maximum rated output current is 2 A and the pin is rated -1.0 V to 18.0 V. |+| 33 | CB4 | passive | Bootstrap pin for the SW4 high-side MOSFET gate drive; CB4 is referenced to SW4 with a maximum of 7.0 V in recommended operating conditions. |+| 34 | ENSW4 | input | Active-high enable input for SW4 with a 2-µA internal pullup; recommended maximum is 3.3 V. |+| 35 | VFB4 | input | Feedback input for SW4; the recommended range is 0.6 V to 1.87 V. |+| 36 | COMP4 | passive | Compensation pin for the SW4 external compensation network; pulling this pin high to VDDA configures the SW3 controller to control both SW3 and SW4. |+| 37 | SS4/PG4 | bidirectional | Soft-start pin for SW4 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD4 signal. |+| 38 | I2CADDR | input | Selects the 7-bit I2C address through a resistor to AGND, sampled only at startup during tRESET_DELAY after the rising edge of CE or RST_N; tying it directly to VDDD is recommended if I2C is not used. |+| 39 | RST_N | input | Digital logic reset; when low, all switchers are disabled, and configuration is reloaded from EEPROM when it is deasserted; recommended range is -0.3 V to 3.3 V. |+| 40 | RCLOCK_SYNC | passive | Resistor input that sets the primary clock frequency from 275 kHz to 2.2 MHz, or serves as the clock sync input; recommended range is -0.3 V to 3.3 V. |+| 41 | I2CALERT | output | Open-drain output pulled low for 200 µs when an I2C watchdog timeout is detected on SDA or SCL; recommended range is -0.3 V to 3.3 V. |+| 42 | SDA | bidirectional | Data input/output pin for the I2C bus; recommended range is -0.3 V to 3.3 V. |+| 43 | SCL | input | Clock input pin for the I2C bus; recommended range is -0.3 V to 3.3 V. |+| 44 | CLK_OUT | output | Clock output, open-collector, which requires a pull-up; recommended range is -0.3 V to 3.3 V. |+| 45 | SS1/PG1 | bidirectional | Soft-start pin for SW1 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD1 signal. |+| 46 | COMP1 | passive | Compensation pin for the SW1 external compensation network; recommended range is -0.3 V to 7.0 V. |+| 47 | VFB1 | input | Feedback input for SW1; the recommended range is 0.6 V to 1.87 V. |+| 48 | ENSW1/ENSEQ | input | Active-high enable input for SW1 (also the sequence start/stop pin in single-enable mode) with a 2-µA internal pullup; recommended maximum is 3.3 V. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Power Management (PMIC) |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `TPS65400RGZT`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `tps65400rgzt-etched.step` / `tps65400rgzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps65400rgzt.step` / `tps65400rgzt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps65400) (80 pp, sha256 `f5ff79cbf2573561`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps65400rgzt-datasheet.pdf)
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CB1 is referenced to SW1 with a maximum of 7.0 V in recommended operating conditions."+ },+ {+ "number": "2",+ "name": "SW1",+ "type": "power_out",+ "description": "Switch pin for SW1; SW1 is rated for -1.0 V to 18.0 V and supplies up to 4 A."+ },+ {+ "number": "3",+ "name": "SW1",+ "type": "power_out",+ "description": "Switch pin for SW1; SW1 is rated for -1.0 V to 18.0 V and supplies up to 4 A."+ },+ {+ "number": "4",+ "name": "SW1",+ "type": "power_out",+ "description": "Switch pin for SW1; SW1 is rated for -1.0 V to 18.0 V and supplies up to 4 A."+ },+ {+ "number": "5",+ "name": "PVIN1",+ "type": "power_in",+ "description": "Power input for the SW1 buck switching regulator, rated 4.5 V to 18 V."+ },+ {+ "number": "6",+ "name": "PVIN2",+ "type": "power_in",+ "description": "Power input for the SW2 buck switching regulator, rated 4.5 V to 18 V."+ },+ {+ "number": "7",+ "name": "PGND1",+ "type": "power_in",+ "description": "Power ground for the buck converters."+ },+ {+ "number": "8",+ "name": "PGND2",+ "type": "power_in",+ "description": "Power ground for the buck converters."+ },+ {+ "number": "9",+ "name": "SW2",+ "type": "power_out",+ "description": "Switch pin for SW2; SW2 is rated for -1.0 V to 18.0 V and supplies up to 4 A."+ },+ {+ "number": "10",+ "name": "SW2",+ "type": "power_out",+ "description": "Switch pin for SW2; SW2 is rated for -1.0 V to 18.0 V and supplies up to 4 A."+ },+ {+ "number": "11",+ "name": "SW2",+ "type": "power_out",+ "description": "Switch pin for SW2; SW2 is rated for -1.0 V to 18.0 V and supplies up to 4 A."+ },+ {+ "number": "12",+ "name": "CB2",+ "type": "passive",+ "description": "Bootstrap pin for the SW2 high-side MOSFET gate drive; CB2 is referenced to SW2 with a maximum of 7.0 V in recommended operating conditions."+ },+ {+ "number": "13",+ "name": "ENSW2",+ "type": "input",+ "description": "Active-high enable input for SW2 with a 2-µA internal pullup; recommended maximum is 3.3 V."+ },+ {+ "number": "14",+ "name": "VFB2",+ "type": "input",+ "description": "Feedback input for SW2; the recommended range is 0.6 V to 1.87 V."+ },+ {+ "number": "15",+ "name": "COMP2",+ "type": "passive",+ "description": "Compensation pin for the SW2 external compensation network; pulling this pin high to VDDA configures the SW1 controller to control both SW1 and SW2."+ },+ {+ "number": "16",+ "name": "SS2/PG2",+ "type": "bidirectional",+ "description": "Soft-start pin for SW2 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD2 signal."+ },+ {+ "number": "17",+ "name": "PGOOD",+ "type": "output",+ "description": "Global power-good output that is by default the logical AND of all switcher PGOOD signals, and goes low if all switchers are disabled."+ },+ {+ "number": "18",+ "name": "VDDG",+ "type": "power_out",+ "description": "Supply for the gate drives, to be bypassed locally to PGND; recommended range is -0.3 V to 7.0 V."+ },+ {+ "number": "19",+ "name": "VDDA",+ "type": "power_out",+ "description": "Output of the internal regulator for analog controls; recommended range is -0.3 V to 7.0 V."+ },+ {+ "number": "20",+ "name": "VDDD",+ "type": "power_out",+ "description": "3.3-V output of the internal regulator for digital controls; recommended range is -0.3 V to 3.3 V."+ },+ {+ "number": "21",+ "name": "AGND",+ "type": "power_in",+ "description": "Ground connection for analog controls."+ },+ {+ "number": "22",+ "name": "VIN",+ "type": "power_in",+ "description": "Analog VIN power input for the VDDD, VDDA, and VGATE subregulators; recommended range is -0.3 V to 18.0 V."+ },+ {+ "number": "23",+ "name": "CE",+ "type": "input",+ "description": "Chip enable with an internal pullup that defaults high when floating; pull low with an open-drain output to disable, since push-pull drive is not recommended, and recommended range is -0.3 V to 7.0 V."+ },+ {+ "number": "24",+ "name": "SS3/PG3",+ "type": "bidirectional",+ "description": "Soft-start pin for SW3 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD3 signal."+ },+ {+ "number": "25",+ "name": "COMP3",+ "type": "passive",+ "description": "Compensation pin for the SW3 external compensation network; recommended range is -0.3 V to 7.0 V."+ },+ {+ "number": "26",+ "name": "VFB3",+ "type": "input",+ "description": "Feedback input for SW3; the recommended range is 0.6 V to 1.87 V."+ },+ {+ "number": "27",+ "name": "ENSW3",+ "type": "input",+ "description": "Active-high enable input for SW3 with a 2-µA internal pullup; recommended maximum is 3.3 V."+ },+ {+ "number": "28",+ "name": "CB3",+ "type": "passive",+ "description": "Bootstrap pin for the SW3 high-side MOSFET gate drive; CB3 is referenced to SW3 with a maximum of 7.0 V in recommended operating conditions."+ },+ {+ "number": "29",+ "name": "SW3",+ "type": "power_out",+ "description": "Switch pin for SW3; the maximum rated output current is 2 A and the pin is rated -1.0 V to 18.0 V."+ },+ {+ "number": "30",+ "name": "PVIN3",+ "type": "power_in",+ "description": "Power input for the SW3 buck switching regulator, rated 4.5 V to 18 V."+ },+ {+ "number": "31",+ "name": "PVIN4",+ "type": "power_in",+ "description": "Power input for the SW4 buck switching regulator, rated 4.5 V to 18 V."+ },+ {+ "number": "32",+ "name": "SW4",+ "type": "power_out",+ "description": "Switch pin for SW4; the maximum rated output current is 2 A and the pin is rated -1.0 V to 18.0 V."+ },+ {+ "number": "33",+ "name": "CB4",+ "type": "passive",+ "description": "Bootstrap pin for the SW4 high-side MOSFET gate drive; CB4 is referenced to SW4 with a maximum of 7.0 V in recommended operating conditions."+ },+ {+ "number": "34",+ "name": "ENSW4",+ "type": "input",+ "description": "Active-high enable input for SW4 with a 2-µA internal pullup; recommended maximum is 3.3 V."+ },+ {+ "number": "35",+ "name": "VFB4",+ "type": "input",+ "description": "Feedback input for SW4; the recommended range is 0.6 V to 1.87 V."+ },+ {+ "number": "36",+ "name": "COMP4",+ "type": "passive",+ "description": "Compensation pin for the SW4 external compensation network; pulling this pin high to VDDA configures the SW3 controller to control both SW3 and SW4."+ },+ {+ "number": "37",+ "name": "SS4/PG4",+ "type": "bidirectional",+ "description": "Soft-start pin for SW4 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD4 signal."+ },+ {+ "number": "38",+ "name": "I2CADDR",+ "type": "input",+ "description": "Selects the 7-bit I2C address through a resistor to AGND, sampled only at startup during tRESET_DELAY after the rising edge of CE or RST_N; tying it directly to VDDD is recommended if I2C is not used."+ },+ {+ "number": "39",+ "name": "RST_N",+ "type": "input",+ "description": "Digital logic reset; when low, all switchers are disabled, and configuration is reloaded from EEPROM when it is deasserted; recommended range is -0.3 V to 3.3 V."+ },+ {+ "number": "40",+ "name": "RCLOCK_SYNC",+ "type": "passive",+ "description": "Resistor input that sets the primary clock frequency from 275 kHz to 2.2 MHz, or serves as the clock sync input; recommended range is -0.3 V to 3.3 V."+ },+ {+ "number": "41",+ "name": "I2CALERT",+ "type": "output",+ "description": "Open-drain output pulled low for 200 µs when an I2C watchdog timeout is detected on SDA or SCL; recommended range is -0.3 V to 3.3 V."+ },+ {+ "number": "42",+ "name": "SDA",+ "type": "bidirectional",+ "description": "Data input/output pin for the I2C bus; recommended range is -0.3 V to 3.3 V."+ },+ {+ "number": "43",+ "name": "SCL",+ "type": "input",+ "description": "Clock input pin for the I2C bus; recommended range is -0.3 V to 3.3 V."+ },+ {+ "number": "44",+ "name": "CLK_OUT",+ "type": "output",+ "description": "Clock output, open-collector, which requires a pull-up; recommended range is -0.3 V to 3.3 V."+ },+ {+ "number": "45",+ "name": "SS1/PG1",+ "type": "bidirectional",+ "description": "Soft-start pin for SW1 by default, with a capacitor setting start-up time; it can be reconfigured through I2C to output the PGOOD1 signal."+ },+ {+ "number": "46",+ "name": "COMP1",+ "type": "passive",+ "description": "Compensation pin for the SW1 external compensation network; recommended range is -0.3 V to 7.0 V."+ },+ {+ "number": "47",+ "name": "VFB1",+ "type": "input",+ "description": "Feedback input for SW1; the recommended range is 0.6 V to 1.87 V."+ },+ {+ "number": "48",+ "name": "ENSW1/ENSEQ",+ "type": "input",+ "description": "Active-high enable input for SW1 (also the sequence start/stop pin in single-enable mode) with a 2-µA internal pullup; recommended maximum is 3.3 V."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The thermal pad is printed as 'PGND(thermal pad)' in the Figure 6-1 pin diagram with note A ('Therma; The datasheet lists SW1 on pins 2, 3 and 4 and SW2 on pins 9, 10 and 11 as one name each; each pin i; COMP2 and COMP4 change controller configuration when pulled high to VDDA (SW1 controls SW1+SW2; SW3 ",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 21,+ "cost_usd": 0.1429,+ "at": "2026-10-08T01:07:37"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps65400",+ "pages": 80,+ "sha256": "f5ff79cbf2573561",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps65400rgzt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps65400rgzt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "932142b0cc4b4027d85150966f5e5b6c994ed3b6e9e27f27e6aa6fbfe7994ad1",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}