component
TPS65265RHBR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS65265RHBR
Texas Instruments · DC-DC Converters · VQFN-32-EP(5x5)
TPS65265RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | V7V | power_out | Internal LDO output 6.1V typical for gate drivers and controller; connect 10µF capacitor to power ground. |
| 2 | PGOOD | tri_state | Open-drain output asserts low if any buck output voltage deviates from 92.5%-107.5% of 0.6V reference due to thermal shutdown, overcurrent, undervoltage, or enable shutdown. |
| 3 | EN1 | input | Enable input for buck1 with 2.9µA internal pullup; float to enable; input UVLO adjustable with external resistor divider. |
| 4 | EN2 | input | Enable input for buck2 with 2.9µA internal pullup; float to enable; input UVLO adjustable with external resistor divider. |
| 5 | EN3 | input | Enable input for buck3 with 2.9µA internal pullup; float to enable; input UVLO adjustable with external resistor divider. |
| 6 | FB2 | input | Feedback Kelvin sensing input for buck2 output voltage; connect to buck2 resistor divider (0.6V reference). |
| 7 | COMP2 | output | Error amplifier output for buck2 loop compensation; connect series RC network for peak current mode control loop. |
| 8 | MODE | input | Mode control input: floating or high for independent buck control via EN1/EN2/EN3; low for automatic power sequencing. |
| 9 | BST2 | power_in | Bootstrap supply for buck2 high-side gate driver; connect 47nF capacitor from BST2 to LX2 (BST-LX UVLO threshold 2.2V). |
| 10 | PGND2 | power_in | Power ground for buck2; connect as close as practical to negative terminal of PVIN2 ceramic capacitor. |
| 11 | LX2 | output | Switching node for buck2 inductor and bootstrap capacitor; voltage swings from one diode drop below ground to PVIN2 voltage. |
| 12 | PVIN2 | power_in | Input power supply for buck2 (4.5V to 17V operating range); connect as close as practical to positive terminal of 10µF ceramic capacitor. |
| 13 | PVIN3 | power_in | Input power supply for buck3 (4.5V to 17V operating range); connect as close as practical to positive terminal of 10µF ceramic capacitor. |
| 14 | LX3 | output | Switching node for buck3 inductor and bootstrap capacitor; voltage swings from one diode drop below ground to PVIN3 voltage. |
| 15 | PGND3 | power_in | Power ground for buck3; connect as close as practical to negative terminal of PVIN3 ceramic capacitor. |
| 16 | BST3 | power_in | Bootstrap supply for buck3 high-side gate driver; connect 47nF capacitor from BST3 to LX3 (BST-LX UVLO threshold 2.2V). |
| 17 | SEQ_DLY | input | Sequencing delay programming pin with 3µA pullup; connect capacitor to set buck power-up sequence interval delay time. |
| 18 | COMP3 | output | Error amplifier output for buck3 loop compensation; connect series RC network for peak current mode control loop. |
| 19 | FB3 | input | Feedback Kelvin sensing input for buck3 output voltage; connect to buck3 resistor divider (0.6V reference). |
| 20 | ROSC | input | Oscillator frequency programming pin; connect external resistor to set switching frequency from 250kHz to 2.3MHz (82.5kΩ sets 610kHz typical). |
| 21 | AGND | power_in | Analog ground common to all buck controllers and analog circuits; connect to power ground plane. |
| 22 | FB1 | input | Feedback Kelvin sensing input for buck1 output voltage; connect to buck1 resistor divider (0.6V reference). |
| 23 | COMP1 | output | Error amplifier output for buck1 loop compensation; connect series RC network for peak current mode control loop. |
| 24 | PG_DLY | input | PGOOD delay programming pin with 3µA pullup; connect external capacitor to set PGOOD assertion delay time (1.5V threshold). |
| 25 | BST1 | power_in | Bootstrap supply for buck1 high-side gate driver; connect 47nF capacitor from BST1 to LX1 (BST-LX UVLO threshold 2.2V). |
| 26 | PGND1 | power_in | Power ground for buck1; connect as close as practical to negative terminal of PVIN1 ceramic capacitor. |
| 27 | PGND1 | power_in | Power ground for buck1 (second ground pin); connect as close as practical to negative terminal of PVIN1 ceramic capacitor. |
| 28 | LX1 | output | Switching node for buck1 inductor and bootstrap capacitor; voltage swings from one diode drop below ground to PVIN1 voltage. |
| 29 | LX1 | output | Switching node for buck1 inductor connection (second pin); voltage swings from one diode drop below ground to PVIN1 voltage. |
| 30 | PVIN1 | power_in | Input power supply for buck1 (4.5V to 17V operating range); connect as close as practical to positive terminal of 22µF ceramic capacitor. |
| 31 | PVIN1 | power_in | Input power supply for buck1 (second connection); connect as close as practical to positive terminal of 22µF ceramic capacitor. |
| 32 | PSM | input | Pulse skipping mode control: tie high or float for PSM operation; tie low for forced continuous current mode (FCCM). |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
TPS65265RHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps65265rhbr-etched.step/tps65265rhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65265rhbr.step/tps65265rhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (49 pp, sha256
00ac4ba9df2800c1, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).