component

TPS65263RHBR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS65263RHBR

Texas Instruments · DC-DC Converters · VQFN-32-EP(5x5)

TPS65263RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN3 input Enable for buck3: float to enable, and a resistor divider on this pin can set the buck3 input UVLO.
2 SDA bidirectional I2C interface data pin, used with the I2C-compatible interface that supports standard mode (100 kHz) and fast mode (400 kHz).
3 SCL input I2C interface clock pin, used with the I2C-compatible interface that supports standard mode (100 kHz) and fast mode (400 kHz).
4 AGND power_in Analog ground common to the buck controllers and other analog circuits; it must be routed separately from high-current power grounds to the (-) terminal of the VIN bypass capacitor.
5 VOUT2 input Buck2 output voltage sense pin.
6 FB2 input Kelvin feedback sensing pin for the buck2 output; connect to the buck2 resistor divider, with a feedback reference of 0.6 V ±1%.
7 COMP2 passive Buck2 error amplifier output and loop compensation pin; connect a series resistor and capacitor to compensate the peak-current PWM loop.
8 SS2 input Buck2 soft-start and tracking input with an internal 5 µA pullup current source; soft-start time is programmed by a capacitor to ground.
9 BST2 passive Bootstrap supply for the buck2 high-side gate driver; connect a capacitor (recommended 47 nF) from BST2 to LX2.
10 LX2 output Buck2 switching node connected to the inductor and bootstrap capacitor; swings from a diode voltage below ground up to the PVIN2 voltage.
11 PGND2 power_in Buck2 power ground; connect as close as practical to the (-) terminal of the PVIN2 input ceramic capacitor.
12 PVIN2 power_in Buck2 input power supply; connect as close as practical to the (+) terminal of an input ceramic capacitor (suggested 10 µF).
13 PVIN3 power_in Buck3 input power supply; connect as close as practical to the (+) terminal of an input ceramic capacitor (suggested 10 µF).
14 PGND3 power_in Buck3 power ground; connect as close as practical to the (-) terminal of the PVIN3 input ceramic capacitor.
15 LX3 output Buck3 switching node connected to the inductor and bootstrap capacitor; swings from a diode voltage below ground up to the PVIN3 voltage.
16 BST3 passive Bootstrap supply for the buck3 high-side gate driver; connect a capacitor (recommended 47 nF) from BST3 to LX3.
17 SS3 input Buck3 soft-start and tracking input with an internal 5 µA pullup current source; soft-start time is programmed by a capacitor to ground.
18 COMP3 passive Buck3 error amplifier output and loop compensation pin; connect a series resistor and capacitor to compensate the peak-current PWM loop.
19 FB3 input Kelvin feedback sensing pin for the buck3 output; connect to the buck3 resistor divider, with a feedback reference of 0.6 V ±1%.
20 VOUT3 input Buck3 output voltage sense pin.
21 VOUT1 input Buck1 output voltage sense pin.
22 FB1 input Kelvin feedback sensing pin for the buck1 output; connect to the buck1 resistor divider, with a feedback reference of 0.6 V ±1%.
23 COMP1 passive Buck1 error amplifier output and loop compensation pin; connect a series resistor and capacitor to compensate the peak-current PWM loop.
24 SS1 input Buck1 soft-start and tracking input with an internal 5 µA pullup current source; soft-start time is programmed by a capacitor to ground.
25 BST1 passive Bootstrap supply for the buck1 high-side gate driver; connect a capacitor (recommended 47 nF) from BST1 to LX1.
26 LX1 output Buck1 switching node connected to the inductor and bootstrap capacitor; swings from a diode voltage below ground up to the PVIN1 voltage.
27 PGND1 power_in Buck1 power ground; connect as close as practical to the (-) terminal of the PVIN1 input ceramic capacitor.
28 PVIN1 power_in Buck1 input power supply; connect as close as practical to the (+) terminal of an input ceramic capacitor (suggested 10 µF).
29 VIN power_in Buck controller power supply; recommended operating range is 4.5 V to 18 V.
30 V7V power_out Internal LDO output for the gate driver and internal controller; connect a 10 µF capacitor from this pin to power ground.
31 EN1 input Enable for buck1: float to enable, and a resistor divider on this pin can set the buck1 input UVLO.
32 EN2 input Enable for buck2: float to enable, and a resistor divider on this pin can set the buck2 input UVLO.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Power Supply Chip
Pins 33

CAD (KiCad official)

  • Symbol: TPS65263RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps65263rhbr-etched.step / tps65263rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps65263rhbr.step / tps65263rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (48 pp, sha256 68fb2fd65d5ab84d, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF