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TPS65185RGZR
Public Made by Adomby adom
Texas Instruments Power Management - Specialized, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS65185RGZR
Texas Instruments · Power Management - Specialized · VQFN-48-EP(7x7)
TPS65185RGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_out | Filter pin for the 2.25-V internal ADC reference; connect a 4.7-µF capacitor from this pin to ground. |
| 2 | INT | output | Open-drain interrupt output, active low. |
| 3 | VNEG | power_out | Negative supply output for panel source drivers; connect a 4.7-µF capacitor from this pin to ground. |
| 4 | VNEG_IN | power_in | Input pin for LDO2 (VNEG); connect a 4.7-µF capacitor from this pin to ground. |
| 5 | WAKEUP | input | Active-high wake-up pin to exit sleep mode; I2C accepts commands once high, but power rails stay disabled until PWRUP is high (93.75-µs deglitch). |
| 6 | DGND | power_in | Digital ground; connect to the ground plane. |
| 7 | INT_LDO | power_out | Filter pin for the 2.7-V internal supply; connect a 4.7-µF capacitor from this pin to ground. |
| 8 | AGND1 | power_in | Analog ground for general analog circuitry. |
| 9 | VNEG_DIS | output | Discharge pin for VNEG; connect to VNEG to discharge it to ground when the rail is disabled, or leave floating if discharge is not wanted. |
| 10 | VIN | power_in | Input power supply for general circuitry (3 V to 6 V recommended input range); connect a 10-µF capacitor from this pin to ground. |
| 11 | N/C | unconnected | Not internally connected. |
| 12 | VCOM_CTRL | input | VCOM enable: pull high to enable the VCOM amplifier; when pulled low with VN enabled, VCOM discharge is enabled (62.52-µs deglitch). |
| 13 | N/C | unconnected | Not internally connected. |
| 14 | VCOM_DIS | input | Discharge pin for VCOM; connect to ground to discharge VCOM when disabled, or leave floating if discharge is not wanted. |
| 15 | VCOM | power_out | Filter pin for the panel common-voltage driver; connect a 4.7-µF capacitor from this pin to ground. |
| 16 | VCOM_PWR | power_in | Internal supply input to the VCOM buffer; connect to the DCDC2 output and place a 4.7-µF capacitor from this pin to ground. |
| 17 | SCL | input | Serial interface (I2C) clock input. |
| 18 | SDA | bidirectional | Serial interface (I2C) data input/output. |
| 19 | VPOS_DIS | input | Discharge pin for VPOS; connect a resistor from VPOS_DIS to VPOS to discharge it when the rail is disabled, or leave floating if discharge is not wanted. |
| 20 | N/C | unconnected | Not internally connected. |
| 21 | PWRUP | input | Power-up pin: pull high to power up all output rails (0-ns deglitch). |
| 22 | PBKG | passive | Die substrate; connect to the VN pin (-16 V) with a short, wide trace to improve heat dissipation. |
| 23 | PWR_GOOD | output | Open-drain power-good output, pulled low when one or more rails are disabled or out of regulation; DCDC1, DCDC2 and VCOM have no effect on it. |
| 24 | VIN_P | power_in | Input supply for the inverting buck-boost converter (DCDC2); connect a 10-µF capacitor from this pin to ground. |
| 25 | VN_SW | output | Switch output of the inverting buck-boost converter (DCDC2). |
| 26 | VN | input | Feedback pin for the inverting buck-boost converter (DCDC2) and supply for the VNEG LDO and VEE charge pump; connect a 4.7-µF capacitor from this pin to ground. |
| 27 | VEE_IN | power_in | Input supply pin for the negative charge pump CP2 (VEE). |
| 28 | VEE_DRV | output | Driver output pin for the negative charge pump CP2 (VEE, -20 V rail). |
| 29 | VEE_DIS | input | Discharge pin for VEE; connect a resistor from VEE_DIS to VEE to discharge it when the rail is disabled, or leave floating if discharge is not wanted. |
| 30 | VEE_D | power_out | Base voltage output of the negative charge pump CP2; connect a 100-nF capacitor from this pin to ground. |
| 31 | VEE_FB | input | Feedback pin for the negative charge pump CP2; rated 0 V to 3.6 V in recommended conditions. |
| 32 | PGND2 | power_in | Power ground for the CP1 (VDDH) and CP2 (VEE) charge pumps. |
| 33 | VDDH_FB | input | Feedback pin for the positive charge pump CP1; rated 0 V to 3.6 V in recommended conditions. |
| 34 | VDDH_D | power_out | Base voltage output of the positive charge pump CP1; connect a 100-nF capacitor from this pin to ground. |
| 35 | VDDH_DIS | input | Discharge pin for VDDH; connect to VDDH to discharge it to ground when the rail is disabled, or leave floating if discharge is not wanted. |
| 36 | VDDH_DRV | output | Driver output pin for the positive charge pump CP1 (VDDH, 22-V rail). |
| 37 | VDDH_IN | power_in | Input supply pin for the positive charge pump CP1 (VDDH). |
| 38 | N/C | unconnected | Not internally connected. |
| 39 | N/C | unconnected | Not internally connected. |
| 40 | VB_SW | output | Switch output of the boost converter (DCDC1). |
| 41 | PGND1 | power_in | Power ground for DCDC1. |
| 42 | VB | power_in | Feedback pin for the boost converter (DCDC1) and supply for the VPOS LDO and VDDH charge pump; connect a 4.7-µF capacitor from this pin to ground. |
| 43 | VPOS_IN | power_in | Input pin for LDO1 (VPOS); connect a 4.7-µF capacitor from this pin to ground. |
| 44 | VPOS | power_out | Positive supply output for panel source drivers; connect a 4.7-µF capacitor from this pin to ground. |
| 45 | VIN3P3 | power_in | Input pin to the 3.3-V power switch (3 V to 6 V recommended input range). |
| 46 | V3P3 | power_out | Output pin of the 3.3-V power switch. |
| 47 | TS | input | Thermistor input; connect a 10-kΩ NTC thermistor and a 43-kΩ linearization resistor between this pin and AGND. |
| 48 | AGND2 | power_in | Reference point for the external thermistor and linearization resistor. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Power Management (PMIC) |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
TPS65185RGZR - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
tps65185rgzr-etched.step/tps65185rgzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65185rgzr.step/tps65185rgzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (66 pp, sha256
903effae4b79ef29, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS65185RGZR
**Texas Instruments** · Power Management - Specialized · VQFN-48-EP(7x7)
TPS65185RGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_out | Filter pin for the 2.25-V internal ADC reference; connect a 4.7-µF capacitor from this pin to ground. |
| 2 | INT | output | Open-drain interrupt output, active low. |
| 3 | VNEG | power_out | Negative supply output for panel source drivers; connect a 4.7-µF capacitor from this pin to ground. |
| 4 | VNEG_IN | power_in | Input pin for LDO2 (VNEG); connect a 4.7-µF capacitor from this pin to ground. |
| 5 | WAKEUP | input | Active-high wake-up pin to exit sleep mode; I2C accepts commands once high, but power rails stay disabled until PWRUP is high (93.75-µs deglitch). |
| 6 | DGND | power_in | Digital ground; connect to the ground plane. |
| 7 | INT_LDO | power_out | Filter pin for the 2.7-V internal supply; connect a 4.7-µF capacitor from this pin to ground. |
| 8 | AGND1 | power_in | Analog ground for general analog circuitry. |
| 9 | VNEG_DIS | output | Discharge pin for VNEG; connect to VNEG to discharge it to ground when the rail is disabled, or leave floating if discharge is not wanted. |
| 10 | VIN | power_in | Input power supply for general circuitry (3 V to 6 V recommended input range); connect a 10-µF capacitor from this pin to ground. |
| 11 | N/C | unconnected | Not internally connected. |
| 12 | VCOM_CTRL | input | VCOM enable: pull high to enable the VCOM amplifier; when pulled low with VN enabled, VCOM discharge is enabled (62.52-µs deglitch). |
| 13 | N/C | unconnected | Not internally connected. |
| 14 | VCOM_DIS | input | Discharge pin for VCOM; connect to ground to discharge VCOM when disabled, or leave floating if discharge is not wanted. |
| 15 | VCOM | power_out | Filter pin for the panel common-voltage driver; connect a 4.7-µF capacitor from this pin to ground. |
| 16 | VCOM_PWR | power_in | Internal supply input to the VCOM buffer; connect to the DCDC2 output and place a 4.7-µF capacitor from this pin to ground. |
| 17 | SCL | input | Serial interface (I2C) clock input. |
| 18 | SDA | bidirectional | Serial interface (I2C) data input/output. |
| 19 | VPOS_DIS | input | Discharge pin for VPOS; connect a resistor from VPOS_DIS to VPOS to discharge it when the rail is disabled, or leave floating if discharge is not wanted. |
| 20 | N/C | unconnected | Not internally connected. |
| 21 | PWRUP | input | Power-up pin: pull high to power up all output rails (0-ns deglitch). |
| 22 | PBKG | passive | Die substrate; connect to the VN pin (-16 V) with a short, wide trace to improve heat dissipation. |
| 23 | PWR_GOOD | output | Open-drain power-good output, pulled low when one or more rails are disabled or out of regulation; DCDC1, DCDC2 and VCOM have no effect on it. |
| 24 | VIN_P | power_in | Input supply for the inverting buck-boost converter (DCDC2); connect a 10-µF capacitor from this pin to ground. |
| 25 | VN_SW | output | Switch output of the inverting buck-boost converter (DCDC2). |
| 26 | VN | input | Feedback pin for the inverting buck-boost converter (DCDC2) and supply for the VNEG LDO and VEE charge pump; connect a 4.7-µF capacitor from this pin to ground. |
| 27 | VEE_IN | power_in | Input supply pin for the negative charge pump CP2 (VEE). |
| 28 | VEE_DRV | output | Driver output pin for the negative charge pump CP2 (VEE, -20 V rail). |
| 29 | VEE_DIS | input | Discharge pin for VEE; connect a resistor from VEE_DIS to VEE to discharge it when the rail is disabled, or leave floating if discharge is not wanted. |
| 30 | VEE_D | power_out | Base voltage output of the negative charge pump CP2; connect a 100-nF capacitor from this pin to ground. |
| 31 | VEE_FB | input | Feedback pin for the negative charge pump CP2; rated 0 V to 3.6 V in recommended conditions. |
| 32 | PGND2 | power_in | Power ground for the CP1 (VDDH) and CP2 (VEE) charge pumps. |
| 33 | VDDH_FB | input | Feedback pin for the positive charge pump CP1; rated 0 V to 3.6 V in recommended conditions. |
| 34 | VDDH_D | power_out | Base voltage output of the positive charge pump CP1; connect a 100-nF capacitor from this pin to ground. |
| 35 | VDDH_DIS | input | Discharge pin for VDDH; connect to VDDH to discharge it to ground when the rail is disabled, or leave floating if discharge is not wanted. |
| 36 | VDDH_DRV | output | Driver output pin for the positive charge pump CP1 (VDDH, 22-V rail). |
| 37 | VDDH_IN | power_in | Input supply pin for the positive charge pump CP1 (VDDH). |
| 38 | N/C | unconnected | Not internally connected. |
| 39 | N/C | unconnected | Not internally connected. |
| 40 | VB_SW | output | Switch output of the boost converter (DCDC1). |
| 41 | PGND1 | power_in | Power ground for DCDC1. |
| 42 | VB | power_in | Feedback pin for the boost converter (DCDC1) and supply for the VPOS LDO and VDDH charge pump; connect a 4.7-µF capacitor from this pin to ground. |
| 43 | VPOS_IN | power_in | Input pin for LDO1 (VPOS); connect a 4.7-µF capacitor from this pin to ground. |
| 44 | VPOS | power_out | Positive supply output for panel source drivers; connect a 4.7-µF capacitor from this pin to ground. |
| 45 | VIN3P3 | power_in | Input pin to the 3.3-V power switch (3 V to 6 V recommended input range). |
| 46 | V3P3 | power_out | Output pin of the 3.3-V power switch. |
| 47 | TS | input | Thermistor input; connect a 10-kΩ NTC thermistor and a 43-kΩ linearization resistor between this pin and AGND. |
| 48 | AGND2 | power_in | Reference point for the external thermistor and linearization resistor. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Power Management (PMIC) |
| Pins | 49 |
## CAD (KiCad official)
- Symbol: `TPS65185RGZR`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `tps65185rgzr-etched.step` / `tps65185rgzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps65185rgzr.step` / `tps65185rgzr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps65185) (66 pp, sha256 `903effae4b79ef29`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps65185rgzr-datasheet.pdf)