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TPS650940A0RSKR

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Texas Instruments Battery Management, QFN-64-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS650940A0RSKR

Texas Instruments · Battery Management · QFN-64-EP(8x8)

TPS650940A0RSKR from Texas Instruments, in a QFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FBGND2 input Remote negative feedback sense for the BUCK2 controller, connected to the VCCGI VSS SENSE signal sent from the SoC to the PMIC.
2 FBVOUT2 input Remote positive feedback sense for the BUCK2 controller, connected to the VCCGI VCC SENSE signal sent from the SoC to the PMIC.
3 DRVH2 output High-side gate driver output for the BUCK2 controller, referenced to VSYS + 5 V.
4 SW2 input Switch node connection for the BUCK2 controller.
5 BOOT2 input Bootstrap pin for the BUCK2 controller; connect a 100-nF ceramic capacitor between this pin and SW2.
6 PGNDSNS2 power_in Power GND connection for BUCK2; connect to the ground terminal of the external low-side FET.
7 DRVL2 output Low-side gate driver output for the BUCK2 controller, 5 V level.
8 DRV5V_2_A1 power_in 5-V supply to the BUCK2 gate driver and LDOA1; bypass to ground with a 2.2-µF (typical) ceramic capacitor, shorted on board to LDO5P0.
9 LDOA1 power_out LDOA1 output, 1.35-3.3 V; bypass to ground with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use.
10 LX3 output Switch node connection for the BUCK3 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR.
11 PVIN3 power_in 5-V power input to the BUCK3 converter; bypass to ground with a 10-µF (typical) ceramic capacitor.
12 FB3 input Remote feedback sense for the BUCK3 converter; connect to the positive terminal of the output capacitor.
13 PMICEN input PMIC cold-boot pin; the rising edge transitions the power state from G3 to S4/S5, and driving it low shuts down all VRs.
14 LDOLS_EN or SWA1_EN input Enable pin for LDOA2, LDOA3 and SWA1 when OTP is configured to LDOLS_EN, or for SWA1 only when OTP is configured to SWA1_EN; resources turn on at assertion (H) and off at deassertion (L).
15 IRQB output Open-drain output interrupt pin; see the IRQ PMIC Interrupt Register for definitions.
16 RSMRSTB output Open-drain always-on-rail power good that reflects a valid state whenever VSYS is available.
17 SWB1 power_out Output of load switch B1, 0.5-3.3 V (1.8 V typical); bypass to ground with a 0.1-µF (typical) ceramic capacitor and short with SWB2.
18 PVINSWB1_B2 power_in Power supply to load switches B1 and B2, 0.5-3.3 V (1.8 V typical); bypass with a 1-µF (typical) ceramic capacitor and connect to ground when not in use.
19 SWB2 power_out Output of load switch B2, 0.5-3.3 V (1.8 V typical); bypass to ground with a 0.1-µF (typical) ceramic capacitor and short with SWB1.
20 LX5 output Switch node connection for the BUCK5 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR.
21 PVIN5 power_in 5-V power input to the BUCK5 converter; bypass to ground with a 10-µF (typical) ceramic capacitor.
22 FB5 input Remote feedback sense for the BUCK5 converter; connect to the positive terminal of the output capacitor.
23 FB4 input Remote feedback sense for the BUCK4 converter; connect to the positive terminal of the output capacitor.
24 PVIN4 power_in 5-V power input to the BUCK4 converter; bypass to ground with a 10-µF (typical) ceramic capacitor.
25 LX4 output Switch node connection for the BUCK4 converter; connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR.
26 GPO output Open-drain output controlled by an I2C GPO_CTRL register bit, usable as an enable signal to an external VR.
27 PCH_PWROK output Open-drain global power good that reflects a valid state whenever VSYS is available.
28 PROCHOT output Optional open-drain output indicating a PMIC thermal event when any die temperature sensor detects the THOT temperature; invert before connecting to the SoC if used, otherwise leave floating.
29 FBVOUT1 input Remote feedback sense for the BUCK1 controller, connected to the VNN VCC SENSE signal sent from the SoC to the PMIC.
30 ILIM1 input Current limit set pin for the BUCK1 controller; fit a resistor from this pin to ground to set the external low-side FET current limit.
31 SWA1 power_out Output of load switch A1, 0.5-3.3 V; bypass to ground with a 0.1-µF (typical) ceramic capacitor and leave floating when not in use.
32 PVINSWA1 power_in Power supply to load switch A1, 0.5-3.3 V; bypass with a 1-µF (typical) ceramic capacitor and connect to ground when not in use.
33 DRVH1 output High-side gate driver output for the BUCK1 controller, referenced to VSYS + 5 V.
34 SW1 input Switch node connection for the BUCK1 controller.
35 BOOT1 input Bootstrap pin for the BUCK1 controller; connect a 100-nF ceramic capacitor between this pin and SW1.
36 PGNDSNS1 power_in Power GND connection for BUCK1; connect to the ground terminal of the external low-side FET.
37 DRVL1 output Low-side gate driver output for the BUCK1 controller, 5 V level.
38 DRV5V_1_6 power_in 5-V supply to the BUCK1 and BUCK6 gate drivers; bypass to ground with a 2.2-µF (typical) ceramic capacitor, shorted on board to LDO5P0.
39 DRVL6 output Low-side gate driver output for the BUCK6 controller, 5 V level.
40 PGNDSNS6 power_in Power GND connection for BUCK6; connect to the ground terminal of the external low-side FET.
41 BOOT6 input Bootstrap pin for the BUCK6 controller; connect a 100-nF ceramic capacitor between this pin and SW6.
42 SW6 input Switch node connection for the BUCK6 controller.
43 DRVH6 output High-side gate driver output for the BUCK6 controller, referenced to VSYS + 5 V.
44 FBVOUT6 input Remote feedback sense for the BUCK6 controller; connect to the positive terminal of the output capacitor.
45 ILIM6 input Current limit set pin for the BUCK6 controller; fit a resistor from this pin to ground to set the external low-side FET current limit.
46 PVINVTT power_in Power supply to the VTT LDO at VDDQ; bypass to ground with a 10-µF (minimum) ceramic capacitor and connect to ground when not in use.
47 VTT power_out Output of the VTT LDO at VDDQ / 2; bypass to ground with 2× 22-µF (minimum) ceramic capacitors and leave floating when not in use.
48 VTTFB input Remote feedback sense for the VTT LDO; connect to the positive terminal of the output capacitor and short to GND when not in use.
49 LDOA3 power_out Output of LDOA3, 0.7-1.5 V; bypass to ground with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use.
50 PVINLDOA2_A3 power_in Power supply to LDOA2 and LDOA3, 1.8 V; bypass to ground with a 4.7-µF (typical) ceramic capacitor and connect to ground when not in use.
51 LDOA2 power_out Output of LDOA2, 0.7-1.5 V; bypass to ground with a 4.7-µF (typical) ceramic capacitor and leave floating when not in use.
52 AGND power_in Analog ground that must not be connected to the thermal pad ground on the top layer and must connect to the ground of the VREF capacitor.
53 VREF power_out 1.25 V band-gap reference output; stabilize by connecting a 100-nF (typical) ceramic capacitor between this pin and quiet ground.
54 LDO3P3 power_out Output of the 3.3-V internal LDO; bypass to ground with a 4.7-µF (typical) ceramic capacitor.
55 VSYS power_in System voltage detection and input to the internal 3.3-V and 5-V LDOs; bypass to ground with a 1-µF (typical) ceramic capacitor.
56 LDO5P0 power_out Output of the 5-V internal LDO or of an internal switch connecting this pin to V5ANA; bypass to ground with a 4.7-µF (typical) ceramic capacitor.
57 V5ANA power_in External 5-V supply input to the internal load switch that connects to LDO5P0; an optional ceramic capacitor improves transient performance.
58 CLK input I2C clock input.
59 DATA bidirectional I2C data line.
60 THERMTRIPB input Thermal shutdown signal from the SoC.
61 SLP_S0B input Power state pin; the PMIC enters Connected Standby at the falling edge and exits at the rising edge.
62 SLP_S3B input Power state pin; the PMIC enters S3 at the falling edge and exits S3 into S0 at the rising edge.
63 SLP_S4B input Power state pin; the PMIC enters S4 at the falling edge and exits S4 into S3 at the rising edge.
64 ILIM2 input Current limit set pin for the BUCK2 controller; fit a resistor from this pin to ground to set the external low-side FET current limit.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-64-EP(8x8)
Category Power Management (PMIC)
Pins 65

CAD (KiCad official)

  • Symbol: TPS650940A0RSKR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • 3D model: QFN-64-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: tps650940a0rskr-etched.step / tps650940a0rskr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps650940a0rskr.step / tps650940a0rskr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (94 pp, sha256 5f0839e7e2610575, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF