# TPS62841DGRR

**Texas Instruments** · DC-DC Converters · HVSSOP-8

TPS62841DGRR from Texas Instruments, in a HVSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOS | input | Output voltage sense pin for the internal feedback divider and regulation loop; it discharges VOUT through an internal MOSFET when the converter is disabled and must be connected directly to the output capacitor with a short trace. |
| 2 | SW | power_out | Switch pin connected to the internal MOSFET switches, where the inductor must be connected. |
| 3 | MODE | input | A low level enables Power-Save Mode with automatic PFM/PWM transition and a high level forces PWM mode; the pin can be toggled during operation and must be terminated. |
| 4 | VSET | input | A resistor to GND sets the output voltage when the converter is enabled, and the external parasitic capacitance at this pin must stay at or below 100 pF. |
| 5 | EN | input | Enable pin: a high level enables the device and a low level turns it off, with an internal pulldown resistor that is active whenever the device is not regulating. |
| 6 | VIN | power_in | Power supply pin with a 1.8 V to 6.5 V input range that requires a 4.7-µF ceramic input capacitor placed close to the pin. |
| 7 | NC | unconnected | Not connected internally; do not connect this pin. |
| 8 | GND | power_in | Ground supply pin that must be connected close to the GND terminals of the input and output capacitors. |
| 9 | EP | power_in | Exposed thermal pad (PowerPAD) that must be connected to GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVSSOP-8 |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Quiescent current into VIN (device not switching, TJ = -40°C to 85°C) | IQ_VIN |  | 36 | 360 | nA | EN = VIN, IOUT = 0µA, VOUT = 1.55V or 1.8V, device not switching, TJ = -40°C to 85°C | 7 |
| Quiescent current into VOS (device not switching, TJ = -40°C to 85°C) | IQ_VOS |  | 56 | 170 | nA | EN = VIN, IOUT = 0µA, VOUT = 1.55V or 1.8V, device not switching, TJ = -40°C to 85°C | 7 |
| Quiescent current into VOS (EN, STOP = VIN, 3V < VOUT < 3.3V) | IQ_VOS |  | 5 | 100 | nA | EN, STOP = VIN, 3V < VOUT < 3.3V, TJ = -40°C to 85°C | 7 |
| STOP mode quiescent current into VIN | IQ_VIN_STOP |  | 70 | 175 | µA | STOP = High, VOUT = 1.8V, TJ = -40°C to 85°C | 7 |
| Shutdown current into VIN | ISD |  | 25 | 300 | nA | EN = GND, VSET = GND, TJ = -40°C to 85°C | 7 |
| Undervoltage lockout threshold, rising VIN | VTH_UVLO+ | 1.72 | 1.8 |  | V | Rising VIN | 7 |
| Undervoltage lockout threshold, falling VIN | VTH_UVLO- | 1.45 | 1.75 |  | V | Falling VIN | 7 |
| High level input voltage (EN, MODE, STOP) | VIH_TH | 1.1 |  |  | V |  | 7 |
| Low level input voltage (EN, MODE, STOP) | VIL_TH |  |  | 0.4 | V |  | 7 |
| Input bias current, MODE input | IIN |  | 1 | 25 | nA | MODE input, TJ = -40°C to 85°C | 7 |
| Internal pull-down resistance (EN, STOP inputs) | RPD | 200 |  | 450 | kΩ | EN, STOP inputs | 7 |
| High-side MOSFET on-resistance (DGR package) | RDS(ON) |  | 460 | 630 | mΩ | VIN = 3.6V, I = 200mA, TJ = -40°C to 85°C | 8 |
| High-side MOSFET on-resistance (DGR package) | RDS(ON) |  | 370 | 495 | mΩ | VIN = 5V, I = 200mA, TJ = -40°C to 85°C | 8 |
| Low-side MOSFET on-resistance (DGR package) | RDS(ON) |  | 200 | 270 | mΩ | VIN = 3.6V, I = 200mA, TJ = -40°C to 85°C | 8 |
| Low-side MOSFET on-resistance (DGR package) | RDS(ON) |  | 165 | 210 | mΩ | VIN = 5V, I = 200mA, TJ = -40°C to 85°C | 8 |
| Soft-start switch current limit | ILIMF_SS | 0.15 | 0.225 | 0.3 | A |  | 8 |
| High-side MOSFET switch current limit | ILIMF | 1 | 1.2 | 1.4 | A |  | 8 |
| Output discharge current into VOS pin | IDISCHARGE_VOS | 16 | 35 | 44 | mA | EN = GND, VOUT = 1.8V, TJ = -40°C to 85°C, over VIN range | 8 |
| Output voltage accuracy (VOUT >= 1.8 V) | VOUT | -1.5 | 0 | 1.5 | % | PWM Mode, IOUT = 0 mA, VOUT >= 1.8 V | 8 |
| Output voltage accuracy (VOUT <= 1.55 V) | VOUT | -2 | 0 | 2 | % | PWM Mode, IOUT = 0 mA, VOUT <= 1.55 V | 8 |
| Reduced current limit soft-start timeout | tSS_ILIMF | 700 |  | 1200 | µs |  | 8 |
| Supply voltage | VIN | 1.8 |  | 6.5 | V |  | 6 |
| Effective inductance | L | 1.51 | 2.2 | 2.9 | µH |  | 6 |
| Effective output capacitance | COUT | 3 | 10 | 40 | µF |  | 6 |
| Effective input capacitance | CIN | 1 | 4.7 |  | µF |  | 6 |
| External parasitic capacitance at VSET pin | CVSET |  |  | 100 | pF |  | 6 |
| Nominal resistance range for external voltage selection resistor (E96 series) | RSET | 0.909 |  | 267 | kΩ | E96 resistor series | 6 |
| External voltage selection resistor tolerance | RSET | -1 | 0 | 1 | % |  | 6 |
| External voltage selection resistor temperature coefficient | RSET | -200 | 0 | 200 | ppm/°C |  | 6 |
| Operating junction temperature range | TJ | -40 |  | 125 | °C |  | 6 |
| Pin voltage VIN | VIN | -0.3 |  | 7 | V |  | 6 |
| Pin voltage SW (DC) | SW | -0.3 |  |  | V | DC; max printed as VIN + 0.3 V | 6 |
| Pin voltage SW (AC) | SW | -2 |  | 8.5 | V | less than 10ns, while switching | 6 |
| Pin voltage EN, MODE, STOP | EN, MODE, STOP | -0.3 |  | 6.5 | V |  | 6 |
| Pin voltage VSET | VSET | -0.3 |  |  | V | Max printed as VIN + 0.3 V with <3.6 V | 6 |
| Pin voltage VOS | VOS | -0.3 |  | 3.7 | V |  | 6 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 6 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 6 |
| Junction-to-ambient thermal resistance (DGR, JEDEC PCB 51-7) | RθJA |  | 54.4 |  | °C/W | 8-pin DGR package | 6 |
| Junction-to-case (top) thermal resistance (DGR) | RθJC(top) |  | 58.1 |  | °C/W | 8-pin DGR package | 6 |
| Junction-to-board thermal resistance (DGR) | RθJB |  | 25.9 |  | °C/W | 8-pin DGR package | 6 |
| Junction-to-top characterization parameter (DGR) | ψJT |  | 1.2 |  | °C/W | 8-pin DGR package | 6 |
| Junction-to-board characterization parameter (DGR) | ψJB |  | 25.9 |  | °C/W | 8-pin DGR package | 6 |
| Junction-to-case (bottom) thermal resistance (DGR) | RθJC(bot) |  | 11.7 |  | °C/W | 8-pin DGR package | 6 |

## CAD (KiCad official)

- Symbol: `TPS62841DGRR`
- Footprint: `Package_SO:HVSSOP-8-1EP_3x3mm_P0.65mm_EP1.57x1.89mm`
- 3D model: HVSSOP-8, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.0 mm nominal HVSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps62841dgrr-etched.step` / `tps62841dgrr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps62841dgrr.step` / `tps62841dgrr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps62840) (45 pp, sha256 `da218f3f1c6e6463`, retrieved 2026-10-09, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps62841dgrr-datasheet.pdf)