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Contents

README

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TPS62152RGTR

Texas Instruments · DC-DC Converters · TQFN-16-EP(3x3)

TPS62152RGTR from Texas Instruments, in a TQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW output Switch node output, -0.3 to 17.3 V; connected to internal MOSFET high-side switch and inductor.
2 SW output Switch node output, -0.3 to 17.3 V; connected to internal MOSFET high-side switch and inductor.
3 SW output Switch node output, -0.3 to 17.3 V; connected to internal MOSFET high-side switch and inductor.
4 PG tri_state Power good open-drain output, -0.3 to 7 V, max sink 10 mA; high when VOUT ready (≥92% nominal), low when below nominal; requires external pullup resistor.
5 FB input Feedback input (fixed 3.3 V version), -0.3 to 7 V; internally pulled down for TPS62152; recommended to connect to AGND for thermal performance.
6 AGND power_in Analog ground reference, 0 V; must be directly connected to exposed thermal pad and common ground plane.
7 FSW input Frequency select input, -0.3 to 7 V; low selects ~2.5 MHz (typ), high selects ~1.25 MHz (typ); internal 400 kΩ pulldown resistor.
8 DEF input Output voltage scaling input, -0.3 to 7 V; low = nominal (3.3 V), high = nominal +5% (3.465 V); internal 400 kΩ pulldown resistor.
9 SS/TR input Soft-start/tracking input, -0.3 to 17.3 V; external capacitor sets output voltage ramp rate (2.5 µA source current typical); can track external voltage for power sequencing.
10 AVIN power_in Analog supply voltage input, -0.3 to 20 V; provides power for control circuitry; must connect to same source as PVIN.
11 PVIN power_in Power supply input, -0.3 to 20 V (recommended 3 to 17 V); supplies power stage and high-side MOSFET gate drive.
12 PVIN power_in Power supply input, -0.3 to 20 V (recommended 3 to 17 V); supplies power stage and high-side MOSFET gate drive.
13 EN input Enable input, -0.3 to 17.3 V; high enables device operation, low enters shutdown (~1.5 µA typ); internal 400 kΩ pulldown resistor.
14 VOS input Output voltage sense input, -0.3 to 7 V; connection point for control loop feedback and feedforward capacitor.
15 PGND power_in Power ground reference, 0 V; must be directly connected to exposed thermal pad and common ground plane.
16 PGND power_in Power ground reference, 0 V; must be directly connected to exposed thermal pad and common ground plane.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

CAD (KiCad official)

  • Symbol: TPS62152RGTR
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: TQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps62152rgtr-etched.step / tps62152rgtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps62152rgtr.step / tps62152rgtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (44 pp, sha256 b146908d5c550566, retrieved 2026-09-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF