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TPS61100PWR

Public Made by Adom

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Texas Instruments DC-DC Converters, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps61100pwrfactory-2.0.0extractor-text
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TPS61100PWR

Texas Instruments · DC-DC Converters · TSSOP-20

TPS61100PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Supply pin; the device starts up from VBAT with an undervoltage lockout at approximately 0.7 V and operates with supply voltages down to 0.8 V.
2 LBI input Low battery comparator input, with the comparator enabled together with EN.
3 ENPB input Pushbutton boost-enable input: 0 (GND) enables the converter and 1 (VBAT) disables it, and a low signal forces start-up while EN is low.
4 EN input Boost-enable input: 1 (VBAT) enables the converter and 0 (GND) puts it into shutdown with the load disconnected from the battery.
5 ADEN input Auto-discharge enable: 1 (VBAT) enables discharge of the output capacitors during shutdown and 0 (GND) disables it.
6 LDOSENSE input LDO feedback input for voltage adjustment; it must be connected to LDOOUT in fixed-output-voltage versions.
7 LDOEN input LDO-enable input: 1 (VBAT) enables the LDO and 0 (GND) disables it.
8 LDOIN input LDO input pin that supplies the integrated 120 mA LDO.
9 LDOOUT output LDO output pin of the integrated second-output regulator.
10 GND power_in Control/logic ground and the reference for all control functions; it must be connected to PGND at only one point close to this pin.
11 PGND power_in Power ground for the boost NMOS switch, kept separate from GND to avoid ground shift from high switch currents.
12 LBO1 output Low battery comparator output 1, an open-drain output.
13 LBO2 output Low battery comparator output 2, an open-drain output.
14 SWN input Boost switch input connected to the internal boost switch node; pin 14 and pin 16 are both SWN and must both be connected.
15 PGOOD output Boost output power-good open-drain output: 1 indicates good and 0 indicates failure.
16 SWN input Boost switch input connected to the internal boost switch node; pin 16 and pin 14 are both SWN and must both be connected.
17 NC unconnected No internal connection on this pin.
18 SKIPEN input Power-save mode enable: 1 (VBAT) enables power save mode and 0 (GND) disables it.
19 VOUT output Boost converter output; the adjustable output is set up to 5.5 V by the external feedback divider.
20 FB input Boost-voltage feedback input for adjustable-output versions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Power Management (PMIC)
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range on VBAT, LBI, SKIPEN, EN, ENPB, ADEN, FB, LDOEN -0.3 3.6 V 7
Input voltage range on SWN, VOUT, LDOIN, LDOOUT, LDOSENSE, PGOOD, LBO1, LBO2 -0.3 7 V 7
Operating free-air temperature range TA -40 85 °C 7
Maximum junction temperature TJ 150 °C 7
Storage temperature range Tstg -65 150 °C 7
Lead temperature 260 °C 1.6 mm from case for 10 s 7
Supply voltage at VBAT VI 0.8 3.3 V 7
Boost inductor L 4.7 10 µH 7
Boost input capacitor Ci 10 µF 7
Boost output capacitor Co 22 100 µF 7
LDO input capacitor Ci 1 µF 7
LDO output capacitor Co 1 2.2 µF 7
Operating virtual junction temperature TJ -40 125 °C 7
Thermal resistance, junction to ambient (20-pin TSSOP, PW) RΘJA 155 K/W PW (TSSOP-20) package 25
Input voltage for start-up VI(b) 0.85 1.1 V RL >= 66 Ω at Vo = 3.3 V 8
Input voltage once started VI(b) 0.8 3.3 V 8
Output voltage Vo(b) 1.5 5.5 V 8
Minimum possible output power 600 mW PW package, VBAT >= 1.5 V 8
Reference voltage Vref 485 500 515 mV 8
Oscillator frequency f 320 500 800 kHz 8
Switch current limit 1200 1500 1800 mA Vo = 3.3 V 8
Startup current limit 610 mA 8
Boost switch on resistance 180 300 mΩ Vo = 3.3 V 8
Sync switch on resistance 180 300 mΩ Vo = 3.3 V 8
Total accuracy (boost output) -3 3 % 8
Auto discharge switch resistance (boost) 400 Ω 8
Boost quiescent current into VBAT 25 40 µA IO = 0 mA, VEN = VBAT = 3.3 V, Vo = 3.3 V, ENLDO = 0 8
Boost quiescent current into VOUT 12 20 µA IO = 0 mA, VEN = VBAT = 3.3 V, Vo = 3.3 V, ENLDO = 0 8
Boost shutdown current 0.5 5 µA VEN = 0 V 8
LDO input voltage range VI(LDO) 1.5 7 V 8
LDO output voltage Vo(LDO) 0.9 3.6 V 8
LDO output current Io(LDO) 120 270 mA VI >= 1.8 V 8
LDO output current Io(LDO) 80 mA VI < 1.8 V 8
LDO short circuit current limit 500 mA 8
Minimum voltage drop (LDO) 300 mV VI >= 1.8 V, Io(LDO) = 120 mA 8
Total accuracy (LDO output) -3 3 % Io >= 1 mA 8
Line regulation (LDO) 0.6 % LDOIN change from 1.8 V to 2.6 V at 100 mA 8
Load regulation (LDO) 0.6 % Load change from 10% to 90% 8
Auto discharge switch resistance (LDO) 400 Ω 8
LDO quiescent current (LDOIN row) 27 40 µA LDOIN = 7 V, VBAT = 1.2 V, EN = 0 8
LDO quiescent current (VBAT row) 27 40 µA LDOIN = 7 V, VBAT = 1.2 V, EN = 0 8
LDO shutdown current 0.01 1 µA 8
LBI1 voltage threshold VIL 390 400 410 mV VLBI voltage decreasing 9
LBI2 voltage threshold VIL 440 450 460 mV VLBI voltage decreasing 9
LBI3 voltage threshold VIL 490 500 510 mV VLBI voltage decreasing 9
LBI input hysteresis 10 mV 9
LBI input current 0.01 0.1 µA EN = Vbat or GND 9
LBO1 output low voltage 0.04 0.4 V Vo = 3.3 V, IOL = 10 µA 9
LBO1 output leakage current 0.01 0.1 µA VLBO = 3.3 V 9
LBO2 output low voltage 0.04 0.4 V Vo = 3.3 V, IOL = 10 µA 9
LBO2 output leakage current 0.01 0.1 µA VLBO = 3.3 V 9
EN, ENPB, LDOEN, SKIPEN and ADEN input low voltage VIL 0.2 × VBAT 9
EN, ENPB, LDOEN, SKIPEN and ADEN input high voltage VIH 0.8 × VBAT 9
EN, ENPB, LDOEN, SKIPEN and ADEN input clamped current 0.01 0.1 µA Clamped on GND or VBAT 9
Powergood threshold 0.9 0.92 0.95 xVo Vo = 3.3 V 9
Powergood output low voltage 0.04 0.4 V Vo = 3.3 V, IOL = 10 µA 9
Powergood output leakage current 0.01 0.1 µA 9
Overtemperature protection 140 °C 9
Overtemperature hysteresis 20 °C 9
Powergood delay 30 µs 9

CAD (KiCad official)

  • Symbol: TPS61100PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: tps61100pwr-etched.step / tps61100pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps61100pwr.step / tps61100pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 bc3d483e43501243, retrieved 2026-10-12, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF