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TPS61030PWPR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, TSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs tps61030pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers tps61030pwpr: viewers · Ray 1mo ago
package.json tps61030pwpr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json tps61030pwpr: specified limits as data (metadata.characteristics, 28 rows from the datasheet) · Ray 25d ago
README.md tps61030pwpr: specified limits as data (metadata.characteristics, 28 rows from the datasheet) · Ray 25d ago
tps61030pwpr-etched.fit.json tps61030pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps61030pwpr-etched.glb tps61030pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps61030pwpr-etched.step tps61030pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps61030pwpr.glb Publish 0.1.0 · Ray 1mo ago
tps61030pwpr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tps61030pwpr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tps61030pwpr.lbr Publish 0.1.0 · Ray 1mo ago
tps61030pwpr.step Publish 0.1.0 · Ray 1mo ago

TPS61030PWPR

Texas Instruments · DC-DC Converters · TSSOP-16-EP

TPS61030PWPR from Texas Instruments, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW passive Boost and rectifying switch input, connects to the external inductor and internal NMOS/PMOS switch pair.
2 SW passive Boost and rectifying switch input, connects to the external inductor and internal NMOS/PMOS switch pair.
3 PGND power_in Power ground; source of the internal NMOS switch, must be connected to system power ground and to the PowerPAD.
4 PGND power_in Power ground; source of the internal NMOS switch, must be connected to system power ground and to the PowerPAD.
5 PGND power_in Power ground; source of the internal NMOS switch, must be connected to system power ground and to the PowerPAD.
6 VBAT power_in Supply voltage input to the device, accepts 1.8 V to 5.5 V.
7 LBI input Low battery comparator input, enabled with EN, switching threshold 500 mV typical, do not let float.
8 SYNC input Enable/disable power save mode (logic high on VBAT disables power save, logic low on GND enables it) or accepts an external clock signal for synchronization.
9 EN input Enable input; logic high (VBAT) enables the converter, logic low (GND) disables it and puts the device in shutdown.
10 LBO output Low battery comparator open-drain output, active low when LBI voltage drops below the 500 mV threshold, high-impedance when device is disabled.
11 GND power_in Control/logic ground reference for all internal control functions; must be connected to PGND at a single point near the IC.
12 FB input Voltage feedback input for adjustable output voltage versions, regulated to an internal reference of 500 mV.
13 VOUT power_out DC/DC converter output, delivers the regulated boost output voltage and current.
14 VOUT power_out DC/DC converter output, delivers the regulated boost output voltage and current.
15 VOUT power_out DC/DC converter output, delivers the regulated boost output voltage and current.
16 NC unconnected No internal connection.
17 PowerPAD power_in Exposed thermal pad; must be soldered to the PCB and connected to PGND for proper power dissipation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16-EP
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VI 1.8 5.5 V 5
TPS61030 output voltage range VO 1.8 5.5 V 5
TPS61030 feedback voltage VFB 490 500 510 mV 5
Oscillator frequency f 500 600 700 kHz 5
Frequency range for synchronization 500 700 kHz 5
Switch current limit 3600 4000 4500 mA VOUT = 5 V 5
Total accuracy -3 3 % 5
Quiescent current into VBAT 10 25 µA IO = 0 mA, VEN = VBAT = 1.8 V, VOUT = 5 V 5
Quiescent current into VOUT 10 20 µA IO = 0 mA, VEN = VBAT = 1.8 V, VOUT = 5 V 5
Shutdown current 0.1 1 µA VEN = 0 V, VBAT = 2.4 V 5
LBI voltage threshold VIL 490 500 510 mV VLBI voltage decreasing 5
LBI input current 0.01 0.1 µA EN = VBAT or GND 5
LBO output low voltage 0.04 0.4 V VO = 3.3 V, IOI = 100 µA 5
LBO output leakage current 0.01 0.1 µA VLBO = 7 V 5
EN, SYNC input current 0.01 0.1 µA Clamped on GND or VBAT 5
Input voltage on LBI VI -0.3 3.6 V 4
Input voltage on SW, VOUT, LBO, VBAT, SYNC, EN, FB -0.3 7 V 4
Maximum junction temperature TJ -40 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage at VBAT VI 1.8 5.5 V 4
Operating ambient temperature range TA -40 85 °C 4
Operating virtual junction temperature range TJ -40 125 °C 4
Junction-to-ambient thermal resistance (PWP) RθJA 46.9 °C/W PWP (16-pin TSSOP) package 4
Junction-to-case (top) thermal resistance (PWP) RθJC(top) 25.8 °C/W PWP (16-pin TSSOP) package 4
Junction-to-board thermal resistance (PWP) RθJB 19.4 °C/W PWP (16-pin TSSOP) package 4
Junction-to-top characterization parameter (PWP) ψJT 0.8 °C/W PWP (16-pin TSSOP) package 4
Junction-to-board characterization parameter (PWP) ψJB 19.3 °C/W PWP (16-pin TSSOP) package 4
Junction-to-case (bottom) thermal resistance (PWP) RθJC(bot) 2.2 °C/W PWP (16-pin TSSOP) package 4

CAD (KiCad official)

  • Symbol: TPS61030PWPR
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: tps61030pwpr-etched.step / tps61030pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps61030pwpr.step / tps61030pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 09d8799e40eac542, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF