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TPS60120PWPR
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Texas Instruments DC-DC Converters, HTSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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tps60120pwpr: specified limits as data (metadata.characteristics, 32 rows from the datasheet)
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TPS60120PWPR
Texas Instruments · DC-DC Converters · HTSSOP-20
TPS60120PWPR from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 2 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 3 | ENABLE | input | Enable input; connect to IN for normal operation, and a logic low turns the device off, reducing supply current to 0.05 µA and disconnecting the output from the input. |
| 4 | FB | input | Feedback input; connect to OUT as close to the load as possible, with an on-chip resistive divider matching the internal 1.21-V reference voltage. |
| 5 | OUT | power_out | Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO. |
| 6 | C1+ | passive | Positive terminal of the flying capacitor C1. |
| 7 | IN | power_in | Supply input for the 1.8-V to 3.6-V range; bypass to PGND with a (CO/2) µF capacitor and connect both IN pins through a short trace. |
| 8 | C1- | passive | Negative terminal of the flying capacitor C1. |
| 9 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 10 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 11 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 12 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 13 | C2- | passive | Negative terminal of the flying capacitor C2. |
| 14 | IN | power_in | Supply input for the 1.8-V to 3.6-V range; connect both IN pins through a short trace. |
| 15 | C2+ | passive | Positive terminal of the flying capacitor C2. |
| 16 | OUT | power_out | Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO. |
| 17 | LBO | output | Low battery detector output (open drain on TPS60120/122/124), which can sink 1 mA and needs a 100-kΩ to 1-MΩ pullup; leave unconnected if not used. |
| 18 | LBI | input | Low battery detector input (TPS60120/122/124 only), compared to the internal 1.21-V reference; connect to ground if the low-battery function is not used. |
| 19 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 20 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (recommended operating) | VI | 1.8 | 3.6 | V | 8 | ||
| Operating junction temperature (recommended) | TJ | 125 | °C | 8 | |||
| Input voltage range (IN, OUT, ENABLE, FB, LBI, LBO/PG) | VI | -0.3 | 5.5 | V | 7 | ||
| Continuous output current (TPS60120) | 300 | mA | TPS60120, TPS60121, TPS60124, TPS60125 | 7 | |||
| Storage temperature range | Tstg | -55 | 150 | °C | 7 | ||
| Lead temperature | 260 | °C | 1.6 mm (1/16 inch) from case for 10 s | 7 | |||
| Maximum junction temperature | TJ | 150 | °C | 7 | |||
| PWP package power rating | 700 | mW | TA ≤ 25°C | 8 | |||
| PWP package power rating | 448 | mW | TA = 70°C | 8 | |||
| PWP package power rating | 364 | mW | TA = 85°C | 8 | |||
| PWP package power rating (case) | 25 | mW | TC ≤ 62.5°C | 8 | |||
| PWP package power rating (case) | 22.9 | mW | TC = 70°C | 8 | |||
| PWP package power rating (case) | 18.5 | mW | TC = 85°C | 8 | |||
| Output voltage | VO | 3.17 | 3.43 | V | TPS60120; 1.8 V < VI < 2 V, 0 < IO < IO(max)/2, TC = 0°C to 70°C | 9 | |
| Internal switching frequency | fOSC(INT) | 210 | 320 | 450 | kHz | VI = 2.4 V | 9 |
| Quiescent current (no-load input current) | IQ | 55 | 90 | µA | VI = 2.4 V | 9 | |
| Shutdown supply current | IQ(SDN) | 0.05 | 1 | µA | VI = 2.4 V, V(ENABLE) = 0 V | 9 | |
| Output leakage current | Ilkg(OUT) | 1 | µA | VI = 2.4 V, V(ENABLE) = 0 V | 9 | ||
| Enable input leakage current | Ilkg(ENABLE) | 0.01 | 0.1 | µA | V(ENABLE) = VGND or VI | 9 | |
| Input undervoltage lockout threshold | V(UVLO) | 1.6 | 1.8 | V | TC = 25°C | 9 | |
| Maximum continuous output current (TPS60120) | IO(MAX) | 200 | mA | TPS60120, TPS60121, TPS60124, TPS60125 | 9 | ||
| Low battery trip voltage (TPS60120) | V(LBITRIP) | 1.15 | 1.21 | 1.27 | V | VI = 1.8 V to 2.2 V, hysteresis 0.8% for rising LBI, TC = 0°C to 70°C | 9 |
| LBI input current (TPS60120) | II(LBI) | 100 | nA | V(LBI) = 1.3 V | 9 | ||
| LBO output voltage low (TPS60120) | VO(LBO) | 0.4 | V | V(LBI) = 0 V, I(LBO,SINK) = 1 mA | 9 | ||
| LBO leakage current (TPS60120) | Ilkg(LBO) | 0.01 | 0.1 | µA | V(LBI) = 1.3 V, V(LBO) = 3.3 V | 9 | |
| Short circuit current limit | 115 | mA | VI < 2.4 V, VO = 0 V, TC = 25°C | 9 | |||
| Output load regulation | 0.003 | %/mA | VI = 2.4 V, 1 mA < IO < IO(MAX), TC = 25°C | 9 | |||
| Output line regulation | 0.3 | %/V | 2 V < VI < 3.3 V, IO = 100 mA, TC = 25°C | 9 | |||
| Junction-to-ambient thermal resistance | RθJA | 178 | °C/W | PWP package | 8 | ||
| Junction-to-case thermal resistance | RθJC | 3.5 | °C/W | PWP package, exposed thermal pad coupled to infinite heat sink | 8 | ||
| Power dissipation derating factor above TA = 25°C | 5.6 | mW/°C | PWP package | 8 | |||
| Power dissipation derating factor above TC = 62.5°C | 285.7 | mW/°C | PWP package | 8 |
CAD (KiCad official)
- Symbol:
TPS60120PWPR - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps60120pwpr-etched.step/tps60120pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps60120pwpr.step/tps60120pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
b856c851bfa4d9f6, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS60120PWPR
**Texas Instruments** · DC-DC Converters · HTSSOP-20
TPS60120PWPR from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 2 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 3 | ENABLE | input | Enable input; connect to IN for normal operation, and a logic low turns the device off, reducing supply current to 0.05 µA and disconnecting the output from the input. |
| 4 | FB | input | Feedback input; connect to OUT as close to the load as possible, with an on-chip resistive divider matching the internal 1.21-V reference voltage. |
| 5 | OUT | power_out | Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO. |
| 6 | C1+ | passive | Positive terminal of the flying capacitor C1. |
| 7 | IN | power_in | Supply input for the 1.8-V to 3.6-V range; bypass to PGND with a (CO/2) µF capacitor and connect both IN pins through a short trace. |
| 8 | C1- | passive | Negative terminal of the flying capacitor C1. |
| 9 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 10 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 11 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 12 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 13 | C2- | passive | Negative terminal of the flying capacitor C2. |
| 14 | IN | power_in | Supply input for the 1.8-V to 3.6-V range; connect both IN pins through a short trace. |
| 15 | C2+ | passive | Positive terminal of the flying capacitor C2. |
| 16 | OUT | power_out | Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO. |
| 17 | LBO | output | Low battery detector output (open drain on TPS60120/122/124), which can sink 1 mA and needs a 100-kΩ to 1-MΩ pullup; leave unconnected if not used. |
| 18 | LBI | input | Low battery detector input (TPS60120/122/124 only), compared to the internal 1.21-V reference; connect to ground if the low-battery function is not used. |
| 19 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 20 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (recommended operating) | VI | 1.8 | | 3.6 | V | | 8 |
| Operating junction temperature (recommended) | TJ | | | 125 | °C | | 8 |
| Input voltage range (IN, OUT, ENABLE, FB, LBI, LBO/PG) | VI | -0.3 | | 5.5 | V | | 7 |
| Continuous output current (TPS60120) | | | | 300 | mA | TPS60120, TPS60121, TPS60124, TPS60125 | 7 |
| Storage temperature range | Tstg | -55 | | 150 | °C | | 7 |
| Lead temperature | | | | 260 | °C | 1.6 mm (1/16 inch) from case for 10 s | 7 |
| Maximum junction temperature | TJ | | | 150 | °C | | 7 |
| PWP package power rating | | | | 700 | mW | TA ≤ 25°C | 8 |
| PWP package power rating | | | | 448 | mW | TA = 70°C | 8 |
| PWP package power rating | | | | 364 | mW | TA = 85°C | 8 |
| PWP package power rating (case) | | | | 25 | mW | TC ≤ 62.5°C | 8 |
| PWP package power rating (case) | | | | 22.9 | mW | TC = 70°C | 8 |
| PWP package power rating (case) | | | | 18.5 | mW | TC = 85°C | 8 |
| Output voltage | VO | 3.17 | | 3.43 | V | TPS60120; 1.8 V < VI < 2 V, 0 < IO < IO(max)/2, TC = 0°C to 70°C | 9 |
| Internal switching frequency | fOSC(INT) | 210 | 320 | 450 | kHz | VI = 2.4 V | 9 |
| Quiescent current (no-load input current) | IQ | | 55 | 90 | µA | VI = 2.4 V | 9 |
| Shutdown supply current | IQ(SDN) | | 0.05 | 1 | µA | VI = 2.4 V, V(ENABLE) = 0 V | 9 |
| Output leakage current | Ilkg(OUT) | | | 1 | µA | VI = 2.4 V, V(ENABLE) = 0 V | 9 |
| Enable input leakage current | Ilkg(ENABLE) | | 0.01 | 0.1 | µA | V(ENABLE) = VGND or VI | 9 |
| Input undervoltage lockout threshold | V(UVLO) | 1.6 | | 1.8 | V | TC = 25°C | 9 |
| Maximum continuous output current (TPS60120) | IO(MAX) | | | 200 | mA | TPS60120, TPS60121, TPS60124, TPS60125 | 9 |
| Low battery trip voltage (TPS60120) | V(LBITRIP) | 1.15 | 1.21 | 1.27 | V | VI = 1.8 V to 2.2 V, hysteresis 0.8% for rising LBI, TC = 0°C to 70°C | 9 |
| LBI input current (TPS60120) | II(LBI) | | | 100 | nA | V(LBI) = 1.3 V | 9 |
| LBO output voltage low (TPS60120) | VO(LBO) | | | 0.4 | V | V(LBI) = 0 V, I(LBO,SINK) = 1 mA | 9 |
| LBO leakage current (TPS60120) | Ilkg(LBO) | | 0.01 | 0.1 | µA | V(LBI) = 1.3 V, V(LBO) = 3.3 V | 9 |
| Short circuit current limit | | | 115 | | mA | VI < 2.4 V, VO = 0 V, TC = 25°C | 9 |
| Output load regulation | | | 0.003 | | %/mA | VI = 2.4 V, 1 mA < IO < IO(MAX), TC = 25°C | 9 |
| Output line regulation | | | 0.3 | | %/V | 2 V < VI < 3.3 V, IO = 100 mA, TC = 25°C | 9 |
| Junction-to-ambient thermal resistance | RθJA | | 178 | | °C/W | PWP package | 8 |
| Junction-to-case thermal resistance | RθJC | | 3.5 | | °C/W | PWP package, exposed thermal pad coupled to infinite heat sink | 8 |
| Power dissipation derating factor above TA = 25°C | | | 5.6 | | mW/°C | PWP package | 8 |
| Power dissipation derating factor above TC = 62.5°C | | | 285.7 | | mW/°C | PWP package | 8 |
## CAD (KiCad official)
- Symbol: `TPS60120PWPR`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps60120pwpr-etched.step` / `tps60120pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps60120pwpr.step` / `tps60120pwpr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps60122) (32 pp, sha256 `b856c851bfa4d9f6`, retrieved 2026-10-12, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps60120pwpr-datasheet.pdf)