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TPS60100PWPR
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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS60100PWPR
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
TPS60100PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 2 | SYNC | input | Selects the clock source: connect to GND to use the internal oscillator, or to IN for external synchronization, in which case the clock is fed through 3V8 and the device operates in regulated 3.3-V mode. |
| 3 | ENABLE | input | Logic-low turns the device off, disconnects the output from the input and reduces supply current to 0.05 µA; ENABLE may go high only when VIN is inside the recommended operating range. |
| 4 | FB | input | Feedback input; connect to OUT as close to the load as possible for best regulation, with an on-chip resistive divider matched to the 1.22-V internal reference. |
| 5 | OUT | power_out | Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO, giving 3.3 V when 3V8 is low and 3.8 V when 3V8 is high. |
| 6 | C1+ | passive | Positive terminal of the charge-pump capacitor C1F. |
| 7 | IN | power_in | Supply input for the 1.8-V to 3.6-V input range; bypass to GND with a (CO/2) µF capacitor and connect both IN pins through a short trace. |
| 8 | C1− | passive | Negative terminal of the charge-pump capacitor C1F. |
| 9 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 10 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 11 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 12 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 13 | C2− | passive | Negative terminal of the charge-pump capacitor C2F. |
| 14 | IN | power_in | Supply input for the 1.8-V to 3.6-V input range; bypass to GND with a (CO/2) µF capacitor and connect both IN pins through a short trace. |
| 15 | C2+ | passive | Positive terminal of the charge-pump capacitor C2F. |
| 16 | OUT | power_out | Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO, giving 3.3 V when 3V8 is low and 3.8 V when 3V8 is high. |
| 17 | SKIP | input | Logic-low selects constant-frequency mode for minimum output ripple and noise; connection to IN selects pulse-skip mode, which gives the lowest quiescent current. |
| 18 | COM | input | Logic-low selects push-pull charge-pump mode to minimize output ripple; connection to IN selects single-ended mode requiring only one flying capacitor. |
| 19 | 3V8 | input | Mode select: logic-low gives the regulated 3.3-V output, while connection to IN gives the preregulated 3.8-V output. |
| 20 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Supply Chip |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS60100PWPR - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps60100pwpr-etched.step/tps60100pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps60100pwpr.step/tps60100pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
5ab67e77c34fa2fd, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS60100PWPR
**Texas Instruments** · DC-DC Converters · HTSSOP-20-EP
TPS60100PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 2 | SYNC | input | Selects the clock source: connect to GND to use the internal oscillator, or to IN for external synchronization, in which case the clock is fed through 3V8 and the device operates in regulated 3.3-V mode. |
| 3 | ENABLE | input | Logic-low turns the device off, disconnects the output from the input and reduces supply current to 0.05 µA; ENABLE may go high only when VIN is inside the recommended operating range. |
| 4 | FB | input | Feedback input; connect to OUT as close to the load as possible for best regulation, with an on-chip resistive divider matched to the 1.22-V internal reference. |
| 5 | OUT | power_out | Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO, giving 3.3 V when 3V8 is low and 3.8 V when 3V8 is high. |
| 6 | C1+ | passive | Positive terminal of the charge-pump capacitor C1F. |
| 7 | IN | power_in | Supply input for the 1.8-V to 3.6-V input range; bypass to GND with a (CO/2) µF capacitor and connect both IN pins through a short trace. |
| 8 | C1− | passive | Negative terminal of the charge-pump capacitor C1F. |
| 9 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 10 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 11 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 12 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |
| 13 | C2− | passive | Negative terminal of the charge-pump capacitor C2F. |
| 14 | IN | power_in | Supply input for the 1.8-V to 3.6-V input range; bypass to GND with a (CO/2) µF capacitor and connect both IN pins through a short trace. |
| 15 | C2+ | passive | Positive terminal of the charge-pump capacitor C2F. |
| 16 | OUT | power_out | Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO, giving 3.3 V when 3V8 is low and 3.8 V when 3V8 is high. |
| 17 | SKIP | input | Logic-low selects constant-frequency mode for minimum output ripple and noise; connection to IN selects pulse-skip mode, which gives the lowest quiescent current. |
| 18 | COM | input | Logic-low selects push-pull charge-pump mode to minimize output ripple; connection to IN selects single-ended mode requiring only one flying capacitor. |
| 19 | 3V8 | input | Mode select: logic-low gives the regulated 3.3-V output, while connection to IN gives the preregulated 3.8-V output. |
| 20 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Supply Chip |
| Pins | 21 |
## CAD (KiCad official)
- Symbol: `TPS60100PWPR`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps60100pwpr-etched.step` / `tps60100pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps60100pwpr.step` / `tps60100pwpr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps60100) (29 pp, sha256 `5ab67e77c34fa2fd`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps60100pwpr-datasheet.pdf)