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TPS60100PWPR
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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+57@@ -0,0 +1,57 @@+# TPS60100PWPR++**Texas Instruments** · DC-DC Converters · HTSSOP-20-EP++TPS60100PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |+| 2 | SYNC | input | Selects the clock source: connect to GND to use the internal oscillator, or to IN for external synchronization, in which case the clock is fed through 3V8 and the device operates in regulated 3.3-V mode. |+| 3 | ENABLE | input | Logic-low turns the device off, disconnects the output from the input and reduces supply current to 0.05 µA; ENABLE may go high only when VIN is inside the recommended operating range. |+| 4 | FB | input | Feedback input; connect to OUT as close to the load as possible for best regulation, with an on-chip resistive divider matched to the 1.22-V internal reference. |+| 5 | OUT | power_out | Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO, giving 3.3 V when 3V8 is low and 3.8 V when 3V8 is high. |+| 6 | C1+ | passive | Positive terminal of the charge-pump capacitor C1F. |+| 7 | IN | power_in | Supply input for the 1.8-V to 3.6-V input range; bypass to GND with a (CO/2) µF capacitor and connect both IN pins through a short trace. |+| 8 | C1− | passive | Negative terminal of the charge-pump capacitor C1F. |+| 9 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |+| 10 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |+| 11 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |+| 12 | PGND | power_in | Power ground carrying the charge-pump current; connect all PGND pins together. |+| 13 | C2− | passive | Negative terminal of the charge-pump capacitor C2F. |+| 14 | IN | power_in | Supply input for the 1.8-V to 3.6-V input range; bypass to GND with a (CO/2) µF capacitor and connect both IN pins through a short trace. |+| 15 | C2+ | passive | Positive terminal of the charge-pump capacitor C2F. |+| 16 | OUT | power_out | Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO, giving 3.3 V when 3V8 is low and 3.8 V when 3V8 is high. |+| 17 | SKIP | input | Logic-low selects constant-frequency mode for minimum output ripple and noise; connection to IN selects pulse-skip mode, which gives the lowest quiescent current. |+| 18 | COM | input | Logic-low selects push-pull charge-pump mode to minimize output ripple; connection to IN selects single-ended mode requiring only one flying capacitor. |+| 19 | 3V8 | input | Mode select: logic-low gives the regulated 3.3-V output, while connection to IN gives the preregulated 3.8-V output. |+| 20 | GND | power_in | Analog ground for the internal reference and control circuitry; connect to PGND through a short trace. |+| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-20-EP |+| Category | Power Supply Chip |+| Pins | 21 |++## CAD (KiCad official)++- Symbol: `TPS60100PWPR`+- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`+- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `tps60100pwpr-etched.step` / `tps60100pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps60100pwpr.step` / `tps60100pwpr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps60100) (29 pp, sha256 `5ab67e77c34fa2fd`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps60100pwpr-datasheet.pdf)
page.jsonadded+279@@ -0,0 +1,279 @@+{+ "slug": "tps60100pwpr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "tps60100pwpr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps60100pwpr.kicad_sym",+ "tps60100pwpr.kicad_mod",+ "tps60100pwpr.glb",+ "tps60100pwpr.step",+ "tps60100pwpr.lbr",+ "docs/hero.png",+ "docs/tps60100pwpr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps60100pwpr-hero.glb",+ "tps60100pwpr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS60100PWPR",+ "manufacturer": "Texas Instruments",+ "package": "HTSSOP-20-EP",+ "pin_count": 21,+ "category": "Power Supply Chip",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps60100",+ "parts": {+ "symbol": "tps60100pwpr.kicad_sym",+ "footprint": "tps60100pwpr.kicad_mod",+ "model_3d": "tps60100pwpr-hero.glb",+ "model_3d_plain": "tps60100pwpr.glb",+ "model_3d_step": "tps60100pwpr-etched.step",+ "model_3d_step_plain": "tps60100pwpr.step",+ "lbr": "tps60100pwpr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2071668",+ "digikey": "296-31985-2-ND",+ "mouser": "595-TPS60100PWPR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:32:27Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-31985-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS60100PWPR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground for the internal reference and control circuitry; connect to PGND through a short trace."+ },+ {+ "number": "2",+ "name": "SYNC",+ "type": "input",+ "description": "Selects the clock source: connect to GND to use the internal oscillator, or to IN for external synchronization, in which case the clock is fed through 3V8 and the device operates in regulated 3.3-V mode."+ },+ {+ "number": "3",+ "name": "ENABLE",+ "type": "input",+ "description": "Logic-low turns the device off, disconnects the output from the input and reduces supply current to 0.05 µA; ENABLE may go high only when VIN is inside the recommended operating range."+ },+ {+ "number": "4",+ "name": "FB",+ "type": "input",+ "description": "Feedback input; connect to OUT as close to the load as possible for best regulation, with an on-chip resistive divider matched to the 1.22-V internal reference."+ },+ {+ "number": "5",+ "name": "OUT",+ "type": "power_out",+ "description": "Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO, giving 3.3 V when 3V8 is low and 3.8 V when 3V8 is high."+ },+ {+ "number": "6",+ "name": "C1+",+ "type": "passive",+ "description": "Positive terminal of the charge-pump capacitor C1F."+ },+ {+ "number": "7",+ "name": "IN",+ "type": "power_in",+ "description": "Supply input for the 1.8-V to 3.6-V input range; bypass to GND with a (CO/2) µF capacitor and connect both IN pins through a short trace."+ },+ {+ "number": "8",+ "name": "C1−",+ "type": "passive",+ "description": "Negative terminal of the charge-pump capacitor C1F."+ },+ {+ "number": "9",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground carrying the charge-pump current; connect all PGND pins together."+ },+ {+ "number": "10",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground carrying the charge-pump current; connect all PGND pins together."+ },+ {+ "number": "11",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground carrying the charge-pump current; connect all PGND pins together."+ },+ {+ "number": "12",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground carrying the charge-pump current; connect all PGND pins together."+ },+ {+ "number": "13",+ "name": "C2−",+ "type": "passive",+ "description": "Negative terminal of the charge-pump capacitor C2F."+ },+ {+ "number": "14",+ "name": "IN",+ "type": "power_in",+ "description": "Supply input for the 1.8-V to 3.6-V input range; bypass to GND with a (CO/2) µF capacitor and connect both IN pins through a short trace."+ },+ {+ "number": "15",+ "name": "C2+",+ "type": "passive",+ "description": "Positive terminal of the charge-pump capacitor C2F."+ },+ {+ "number": "16",+ "name": "OUT",+ "type": "power_out",+ "description": "Regulated power output; connect both OUT pins through a short trace and bypass to GND with the output filter capacitor CO, giving 3.3 V when 3V8 is low and 3.8 V when 3V8 is high."+ },+ {+ "number": "17",+ "name": "SKIP",+ "type": "input",+ "description": "Logic-low selects constant-frequency mode for minimum output ripple and noise; connection to IN selects pulse-skip mode, which gives the lowest quiescent current."+ },+ {+ "number": "18",+ "name": "COM",+ "type": "input",+ "description": "Logic-low selects push-pull charge-pump mode to minimize output ripple; connection to IN selects single-ended mode requiring only one flying capacitor."+ },+ {+ "number": "19",+ "name": "3V8",+ "type": "input",+ "description": "Mode select: logic-low gives the regulated 3.3-V output, while connection to IN gives the preregulated 3.8-V output."+ },+ {+ "number": "20",+ "name": "GND",+ "type": "power_in",+ "description": "Analog ground for the internal reference and control circuitry; connect to PGND through a short trace."+ },+ {+ "number": "21",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed PowerPAD thermal pad is shown in Figure 2 but is not a numbered terminal in the datashee; The datasheet does not assign I/O types to the charge-pump terminals C1+, C1−, C2+ and C2−; they wer; Only the pin table on page 2 and the package/ordering pages were available in the supplied text (9 o",+ "exposed pad 21 added from the footprint"+ ],+ "pages_sent": 9,+ "cost_usd": 0.0694,+ "at": "2026-10-08T15:31:51"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps60100",+ "pages": 29,+ "sha256": "5ab67e77c34fa2fd",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 21,+ "described": 21,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps60100pwpr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.41,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f25728c0f84a3c1c77cd32221bb32551442b0ccc492dfd30173a3fa9a20e1adb",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps60100pwpr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.41,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9129bc8748695ad2c3c29ae1492c4d7402a31ae121f54a485a3968ab919a51fe",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}