# TPS56428DDAR

**Texas Instruments** · DC-DC Converters · SOIC-8-EP

TPS56428DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable input, active high; it must be pulled up to enable the device, with EN high-level input voltage of 1.6 V minimum and EN low-level input voltage of 0.6 V maximum, and recommended input range of -0.1 V to 18 V. |
| 2 | VFB | input | Converter feedback input, connected to the output voltage through a feedback resistor divider, with a recommended input range of -0.1 V to 5.5 V. |
| 3 | VREG5 | power_out | 5.5 V power supply output that requires a capacitor (typically 0.47 µF) to GND, is not active when EN is low, and is rated for 0 to 5 mA output current. |
| 4 | PG | output | Open-drain power good output, with a recommended voltage range of -0.1 V to 5.7 V. |
| 5 | GND | power_in | Ground pin and power ground return for the switching circuit; sensitive SS and VFB returns must be connected to GND at a single point. |
| 6 | SW | power_out | Switch node connection between the high-side and low-side NFETs, with a recommended range of -1.8 V to 18 V (10 ns transient -3 V to 21 V). |
| 7 | VBST | power_in | Supply input for the high-side FET gate drive; a 0.1 µF capacitor must be connected between VBST and SW, with recommended VBST vs SW range of -0.1 V to 6.0 V. |
| 8 | VIN | power_in | Input voltage supply pin, with a supply input voltage range of 4.5 V to 18 V. |
| 9 | Exposed Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |

## CAD (KiCad official)

- Symbol: `TPS56428DDAR`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `tps56428ddar-etched.step` / `tps56428ddar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps56428ddar.step` / `tps56428ddar.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps56428) (31 pp, sha256 `05e2ec18aaa51bb4`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps56428ddar-datasheet.pdf)