component
TPS56428DDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+46@@ -0,0 +1,46 @@+# TPS56428DDAR++**Texas Instruments** · DC-DC Converters · SOIC-8-EP++TPS56428DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | EN | input | Enable input, active high; it must be pulled up to enable the device, with EN high-level input voltage of 1.6 V minimum and EN low-level input voltage of 0.6 V maximum, and recommended input range of -0.1 V to 18 V. |+| 2 | VFB | input | Converter feedback input, connected to the output voltage through a feedback resistor divider, with a recommended input range of -0.1 V to 5.5 V. |+| 3 | VREG5 | power_out | 5.5 V power supply output that requires a capacitor (typically 0.47 µF) to GND, is not active when EN is low, and is rated for 0 to 5 mA output current. |+| 4 | PG | output | Open-drain power good output, with a recommended voltage range of -0.1 V to 5.7 V. |+| 5 | GND | power_in | Ground pin and power ground return for the switching circuit; sensitive SS and VFB returns must be connected to GND at a single point. |+| 6 | SW | power_out | Switch node connection between the high-side and low-side NFETs, with a recommended range of -1.8 V to 18 V (10 ns transient -3 V to 21 V). |+| 7 | VBST | power_in | Supply input for the high-side FET gate drive; a 0.1 µF capacitor must be connected between VBST and SW, with recommended VBST vs SW range of -0.1 V to 6.0 V. |+| 8 | VIN | power_in | Input voltage supply pin, with a supply input voltage range of 4.5 V to 18 V. |+| 9 | Exposed Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-8-EP |+| Category | Power Management (PMIC) |+| Pins | 9 |++## CAD (KiCad official)++- Symbol: `TPS56428DDAR`+- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`+- 3D model: SOIC-8-EP (KiCad packages3D, STEP)+- 3D model files: `tps56428ddar-etched.step` / `tps56428ddar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps56428ddar.step` / `tps56428ddar.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps56428) (31 pp, sha256 `05e2ec18aaa51bb4`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps56428ddar-datasheet.pdf)
page.jsonadded+207@@ -0,0 +1,207 @@+{+ "slug": "tps56428ddar",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps56428ddar",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps56428ddar.kicad_sym",+ "tps56428ddar.kicad_mod",+ "tps56428ddar.glb",+ "tps56428ddar.step",+ "tps56428ddar.lbr",+ "docs/hero.png",+ "docs/tps56428ddar-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps56428ddar-hero.glb",+ "tps56428ddar-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS56428DDAR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-8-EP",+ "pin_count": 9,+ "category": "Power Management (PMIC)",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps56428",+ "parts": {+ "symbol": "tps56428ddar.kicad_sym",+ "footprint": "tps56428ddar.kicad_mod",+ "model_3d": "tps56428ddar-hero.glb",+ "model_3d_plain": "tps56428ddar.glb",+ "model_3d_step": "tps56428ddar-etched.step",+ "model_3d_step_plain": "tps56428ddar.step",+ "lbr": "tps56428ddar.lbr"+ },+ "distributor_links": {+ "lcsc": "C86168",+ "digikey": "296-35856-2-ND",+ "mouser": "595-TPS56428DDAR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T01:53:01Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-35856-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS56428DDAR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "EN",+ "type": "input",+ "description": "Enable input, active high; it must be pulled up to enable the device, with EN high-level input voltage of 1.6 V minimum and EN low-level input voltage of 0.6 V maximum, and recommended input range of -0.1 V to 18 V."+ },+ {+ "number": "2",+ "name": "VFB",+ "type": "input",+ "description": "Converter feedback input, connected to the output voltage through a feedback resistor divider, with a recommended input range of -0.1 V to 5.5 V."+ },+ {+ "number": "3",+ "name": "VREG5",+ "type": "power_out",+ "description": "5.5 V power supply output that requires a capacitor (typically 0.47 µF) to GND, is not active when EN is low, and is rated for 0 to 5 mA output current."+ },+ {+ "number": "4",+ "name": "PG",+ "type": "output",+ "description": "Open-drain power good output, with a recommended voltage range of -0.1 V to 5.7 V."+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin and power ground return for the switching circuit; sensitive SS and VFB returns must be connected to GND at a single point."+ },+ {+ "number": "6",+ "name": "SW",+ "type": "power_out",+ "description": "Switch node connection between the high-side and low-side NFETs, with a recommended range of -1.8 V to 18 V (10 ns transient -3 V to 21 V)."+ },+ {+ "number": "7",+ "name": "VBST",+ "type": "power_in",+ "description": "Supply input for the high-side FET gate drive; a 0.1 µF capacitor must be connected between VBST and SW, with recommended VBST vs SW range of -0.1 V to 6.0 V."+ },+ {+ "number": "8",+ "name": "VIN",+ "type": "power_in",+ "description": "Input voltage supply pin, with a supply input voltage range of 4.5 V to 18 V."+ },+ {+ "number": "9",+ "name": "Exposed Thermal Pad",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed thermal pad (back side of the package) is not a numbered pin in the datasheet. It is not; Pin numbers were taken from the PIN FUNCTIONS table on page 5 because the DEVICE INFORMATION top-vie",+ "exposed pad 9 added from the footprint"+ ],+ "pages_sent": 9,+ "cost_usd": 0.0553,+ "at": "2026-10-08T01:52:46"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps56428",+ "pages": 31,+ "sha256": "05e2ec18aaa51bb4",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 9,+ "described": 9,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps56428ddar.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 4.9,+ 1.55+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "2d6f7e774e8143e3320cbd59eb5be9f3b7864614644e3b072006e1eb05fb7fa6",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps56428ddar-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 4.9,+ 1.55+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "07c20426e216bacad73f4a61e7e8da3833eaa6b0e558088e94fc909ddef93dc0",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}