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TPS54628DDAR

Texas Instruments · DC-DC Converters · SOIC-8-EP

TPS54628DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable input control; EN is active high and must be pulled up to enable the device, with a recommended input range of -0.1 V to 18 V.
2 VFB input Converter feedback input, connected to the output voltage through a feedback resistor divider, with a recommended range of -0.1 V to 5.5 V.
3 VREG5 power_out 5.5 V internal supply output that requires a typical 1 µF capacitor to GND, is not active when EN is low, and is rated for an output current of 0 to 5 mA.
4 SS passive Soft-start control pin where an external capacitor to GND sets the start-up ramp, sourced by a 6 µA typical charge current, with a recommended range of -0.1 V to 5.7 V.
5 GND power_in Ground pin and power ground return for the switching circuit, which must be connected to the exposed thermal pad and returned at a single point for the sensitive SS and VFB returns.
6 SW power_out Switch node between the high-side and low-side NFETs, with a recommended range of -1.8 V to 18 V (10 ns transient -3 V to 21 V).
7 VBST power_in Supply input for the high-side FET gate drive, which requires a 0.1 µF capacitor between VBST and SW, with a recommended VBST-to-SW range of -0.1 V to 6.0 V.
8 VIN power_in Input voltage supply pin with a recommended operating range of 4.5 V to 18 V.
9 PowerPAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN, EN VIN, EN -0.3 20 V 2
Input voltage range VBST VBST -0.3 26 V 2
Input voltage range VBST (10 ns transient) VBST -0.3 28 V 10 ns transient 2
Input voltage range VBST (vs SW) VBST (vs SW) -0.3 6.5 V 2
Input voltage range VFB, SS VFB, SS -0.3 6.5 V 2
Input voltage range SW SW -2 20 V 2
Input voltage range SW (10 ns transient) SW -3 22 V 10 ns transient 2
Output voltage range VREG5 VREG5 -0.3 6.5 V 2
Output voltage range GND GND -0.3 0.3 V 2
Voltage from GND to thermal pad Vdiff -0.2 0.2 V 2
Electrostatic discharge Human Body Model (HBM) 2 kV 2
Electrostatic discharge Charged Device Model (CDM) 500 V 2
Operating junction temperature TJ -40 150 °C 2
Storage temperature Tstg -55 150 °C 2
Supply input voltage range VIN 4.5 18 V 3
Input voltage range VBST VBST -0.1 24 V 3
Input voltage range VBST (10 ns transient) VBST -0.1 27 V 10 ns transient 3
Input voltage range VBST (vs SW) VBST(vs SW) -0.1 6 V 3
Input voltage range SS SS -0.1 5.7 V 3
Input voltage range EN EN -0.1 18 V 3
Input voltage range VFB VFB -0.1 5.5 V 3
Input voltage range SW SW -1.8 18 V 3
Input voltage range SW (10 ns transient) SW -3 21 V 10 ns transient 3
Input voltage range GND GND -0.1 0.1 V 3
Output voltage range VREG5 VREG5 -0.1 5.7 V 3
Output current range IVREG5 IO 0 5 mA 3
Operating free-air temperature TA -40 85 °C 3
Operating junction temperature TJ -40 150 °C 3
VIN current, operating non-switching supply current IVIN 950 1400 μA TA = 25°C, EN = 5 V, VFB = 0.8 V 3
VIN current, shutdown supply current IVINSDN 3 10 μA TA = 25°C, EN = 0 V 3
EN pin resistance to GND REN 200 400 800 kΩ VEN = 12 V 3
VFB threshold voltage (continuous mode, 25°C) VFBTH 757 765 773 mV TA = 25°C, VO = 1.05 V, continuous mode operation 3
VFB threshold voltage (continuous mode, -40 to 85°C) VFBTH 751 765 779 mV TA = -40 to 85°C, VO = 1.05 V, continuous mode operation 3
VFB input current IVFB -0.15 0 0.15 μA VFB = 0.8 V, TA = 25°C 3
VREG5 output voltage VVREG5 5.2 5.5 5.7 V TA = 25°C, 6 V < VIN < 18 V, 0 < IVREG5 < 5 mA 3
UVLO wake up VREG5 voltage 3.45 3.75 4.05 V 4
UVLO hysteresis VREG5 voltage 0.13 0.32 0.48 V 4
Current limit IOCL 6.7 7.3 8.9 A L out = 1.5 μH 3
SS charge current ISS 4.2 6 7.8 μA VSS = 1 V 4
EN high-level input voltage VEN 1.6 V 3
EN low-level input voltage VEN 0.6 V 3
VFB threshold voltage (Eco-mode) VFBTH 772 mV TA = 25°C, VO = 1.05 V, IO = 10 mA, Eco-mode operation 3
Output current IVREG5 20 mA VIN = 6 V, VREG5 = 4.0 V, TA = 25°C 3
High side switch resistance RDS(on) 36 mΩ 25°C, VBST - SW = 5.5 V 3
Low side switch resistance RDS(on) 28 mΩ 25°C 3
Thermal shutdown threshold TSDN 165 °C 4
Thermal shutdown hysteresis 35 °C 4
On time tON 150 ns VIN = 12 V, VO = 1.05 V 4
Output OVP threshold VOVP 125 % OVP Detect (L > H) 4
Output hiccup threshold VHICCUP 65 % Hiccup detect (H > L) 4
Output hiccup delay THICCUPDELAY 250 µsec To hiccup state 4
Output hiccup enable delay THICCUPENDELAY 1.7 x Relative to soft-start time 4
Junction-to-ambient thermal resistance θJA 43.5 °C/W 2
Junction-to-case (top) thermal resistance θJCtop 49.4 °C/W 2
Junction-to-board thermal resistance θJB 25.6 °C/W 2
Junction-to-top characterization parameter ψJT 7.4 °C/W 2
Junction-to-board characterization parameter ψJB 25.5 °C/W 2
Junction-to-case (bottom) thermal resistance θJCbot 5.2 °C/W 2

CAD (KiCad official)

  • Symbol: TPS54628DDAR
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: tps54628ddar-etched.step / tps54628ddar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54628ddar.step / tps54628ddar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 842f26cf9d65474f, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF