Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

TPS54418RTER

Texas Instruments · DC-DC Converters · WQFN-16-EP(3x3)

TPS54418RTER from Texas Instruments, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input supply voltage with operating range from 2.95 V to 6 V.
2 VIN power_in Input supply voltage with operating range from 2.95 V to 6 V.
3 GND power_in Power ground, should be connected directly to the exposed power pad under the device.
4 GND power_in Power ground, should be connected directly to the exposed power pad under the device.
5 AGND power_in Analog ground, should be electrically connected to GND close to the device.
6 VSENSE input Inverting input of the transconductance error amplifier connected to resistor divider from output voltage.
7 COMP output Error amplifier output with frequency compensation components connected; internally compared to switch current.
8 RT/CLK input Resistor timing or external clock input: 85 kΩ to 1000 kΩ resistor sets switching frequency from 200 kHz to 2000 kHz, or external clock with minimum 75 ns pulse width.
9 SS input Soft-start pin where external capacitor sets output voltage rise time; charged by 1.8 μA internal current source.
10 PH output Switching node connecting the source of the high-side power MOSFET and drain of the low-side synchronous rectifier MOSFET.
11 PH output Switching node connecting the source of the high-side power MOSFET and drain of the low-side synchronous rectifier MOSFET.
12 PH output Switching node connecting the source of the high-side power MOSFET and drain of the low-side synchronous rectifier MOSFET.
13 BOOT input Bootstrap supply pin requiring 0.1 μF ceramic capacitor between BOOT and PH; monitored by UVLO with 2.1 V minimum threshold at 2.95 V input.
14 PWRGD output Open-drain power good output pulled low when VSENSE falls below 93% or rises above 107% of 0.8 V reference.
15 EN input Enable pin with internal pull-up current source; pull below 1.25 V threshold to disable; external resistors adjust UVLO.
16 VIN power_in Input supply voltage with operating range from 2.95 V to 6 V.
17 Thermal Pad power_in Exposed power pad soldered to PCB ground plane with multiple vias for thermal and mechanical performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

CAD (KiCad official)

  • Symbol: TPS54418RTER
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps54418rter-etched.step / tps54418rter-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54418rter.step / tps54418rter.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 d86efb2911352e10, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF