component
TPS54394PWPR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-16-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54394PWPR
Texas Instruments · DC-DC Converters · HTSSOP-16-EP
TPS54394PWPR from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN1 | power_in | Power input for both channels, rated 4.5V to 18V, connected to high-side NFET drains. |
| 2 | VBST1 | power_in | Bootstrap supply for channel 1 high-side FET gate driver; connect 0.1µF ceramic capacitor between VBST1 and SW1. |
| 3 | SW1 | output | Switch node output for channel 1 at junction of high-side and low-side FETs; input of current comparator. |
| 4 | PGND1 | power_in | Power ground return for channel 1 low-side MOSFET; used as reference for current sensing via SWx-PGNDx voltage measurement. |
| 5 | EN1 | input | Enable input for channel 1; pull above 2.0V to enable converter or below 0.4V to disable. |
| 6 | PG1 | output | Open-drain power good output for channel 1; goes high when output within ±16% of target after 1.5ms delay, goes low after 2µs if out of regulation. |
| 7 | VFB1 | input | D-CAP2 feedback input for channel 1; connect output voltage via resistor divider to set output voltage at 0.765V nominal. |
| 8 | GND | power_in | Signal ground; connect sensitive feedback and soft-start signal returns at a single point. |
| 9 | VREG5 | power_out | 5.5V linear regulator output; bypass with ≥1µF ceramic capacitor to GND (active when EN is high). |
| 10 | VFB2 | input | D-CAP2 feedback input for channel 2; connect output voltage via resistor divider to set output voltage at 0.765V nominal. |
| 11 | PG2 | output | Open-drain power good output for channel 2; goes high when output within ±16% of target after 1.5ms delay, goes low after 2µs if out of regulation. |
| 12 | EN2 | input | Enable input for channel 2; pull above 2.0V to enable converter or below 0.4V to disable. |
| 13 | PGND2 | power_in | Power ground return for channel 2 low-side MOSFET; used as reference for current sensing via SWx-PGNDx voltage measurement. |
| 14 | SW2 | output | Switch node output for channel 2 at junction of high-side and low-side FETs; input of current comparator. |
| 15 | VBST2 | power_in | Bootstrap supply for channel 2 high-side FET gate driver; connect 0.1µF ceramic capacitor between VBST2 and SW2. |
| 16 | VIN2 | power_in | Power input for 5.5V linear regulator, rated 4.5V to 18V. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16-EP |
| Category | Power Supply Chip |
| Pins | 17 |
CAD (KiCad official)
- Symbol:
TPS54394PWPR - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
tps54394pwpr-etched.step/tps54394pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54394pwpr.step/tps54394pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
d048a180d36720dd, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).