component

TPS54335ADDAR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, SOP-8-EP-150mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs tps54335addar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json footprint + symbol: give this part its thermal pad. It shipped SOIC-8_3.9x4.9mm_P1.27mm, which has no exposed pad at al… · Ray
page.json tps54335addar: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md tps54335addar: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
tps54335addar-etched.fit.json tps54335addar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tps54335addar-etched.glb tps54335addar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tps54335addar-etched.step tps54335addar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tps54335addar.glb Publish 0.1.0 · Ray
tps54335addar.kicad_mod footprint + symbol: give this part its thermal pad. It shipped SOIC-8_3.9x4.9mm_P1.27mm, which has no exposed pad at al… · Ray
tps54335addar.kicad_sym footprint + symbol: give this part its thermal pad. It shipped SOIC-8_3.9x4.9mm_P1.27mm, which has no exposed pad at al… · Ray
tps54335addar.lbr footprint + symbol: give this part its thermal pad. It shipped SOIC-8_3.9x4.9mm_P1.27mm, which has no exposed pad at al… · Ray
tps54335addar.step Publish 0.1.0 · Ray

TPS54335ADDAR

Texas Instruments · DC-DC Converters · SOP-8-EP-150mil

TPS54335ADDAR from Texas Instruments, in a SOP-8-EP-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT output Bootstrap capacitor node for the high-side MOSFET gate driver. A bootstrap capacitor is required between BOOT and PH. If the BOOT-PH voltage falls below the BOOT-PH UVLO (~2.1-3 V), switching is inhibited until the capacitor is refreshed.
2 VIN power_in Supply input voltage, 4.5 V to 28 V (30 V abs max). Bypass with a low-ESR ceramic capacitor placed close to the VIN and GND pins.
3 PH output Switch node (source of the internal high-side power MOSFET / drain of the low-side MOSFET). Connect to the output inductor and to the low side of the bootstrap capacitor. Rated -1 V to 30 V (-3.5 V for 10 ns transients).
4 GND power_in Device ground. Must be tied to the exposed PowerPAD for proper operation and thermal performance.
5 VSENSE input Inverting input of the transconductance (gm) error amplifier. Connect to the feedback resistor divider from VOUT; the internal reference is 0.8 V (±0.8%).
6 COMP output Error-amplifier output and input to the output switch current comparator. Connect frequency-compensation network (R-C, optional C) to GND to set loop response.
7 EN input Enable input. Float to enable (internal pull-up). Enable threshold typ 1.21 V rising / 1.17 V falling. Can be driven by a resistor divider from VIN to program a precision input UVLO.
8 RT input Switching-frequency programming pin. Connect an external resistor from RT to GND to set the switching frequency (50 kHz to 1.5 MHz; e.g. ~480 kHz with 100 kΩ).
PAD PowerPAD power_in Exposed thermal pad on the underside of the package. Must be soldered to the PCB and connected to GND (pin 4) with multiple thermal vias to a ground plane for correct operation and thermal dissipation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOP-8-EP-150mil
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • TPS54335ADDAR
  • TPS54335ADDARDRC
  • TPS54335ADDARDRCR
  • TPS54335ADDARDRCT
  • TPS54335ADDARDDA (TPS54336A)

CAD (KiCad official)

  • Symbol: TPS54335ADDAR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8-EP-150mil (KiCad packages3D, STEP)
  • 3D model files: tps54335addar-etched.step / tps54335addar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54335addar.step / tps54335addar.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tps54335addar.step 122 KB You want the bare part, or you mark your own boards.
tps54335addar-etched.step 2.7 MB You want the part with TPS54335ADDAR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 659 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (52 pp, sha256 35ab1bac1ea6973b, retrieved 2026-08-17, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF