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TPS54329DDAR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS54329DDAR

Texas Instruments · DC-DC Converters · SOIC-8-EP

TPS54329DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBST power_in Bootstrap supply for high-side FET gate drive; connect 0.1µF capacitor between VBST and SW pins, with internal diode to VREG5.
2 VIN power_in Input voltage supply pin.
3 SW output Switch node connection between high-side NFET and low-side NFET.
4 GND power_in Power ground return for switching circuit; connect sensitive SS and VFB returns at a single point.
5 VFB input Converter feedback input; connect to output voltage with feedback resistor divider.
6 VREG5 power_out 5.5 V regulated power supply output; connect 0.47µF capacitor to GND (inactive when EN is low).
7 EN input Enable input control (active high); must be pulled up to enable the device.
8 SS input Soft-start control; connect external capacitor to GND for adjustable soft-start time.
9 Exposed Thermal Pad power_in Thermal pad for heat dissipation; must be soldered to PCB and connected to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range, VIN, EN VIN, EN -0.3 20 V 2
Input voltage range, VBST VBST -0.3 26 V 2
Input voltage range, VBST (10 ns transient) VBST -0.3 28 V 10 ns transient 2
Input voltage range, VBST (vs SW) VBST (vs SW) -0.3 6.5 V 2
Input voltage range, VFB, SS VFB, SS -0.3 6.5 V 2
Input voltage range, SW SW -2 20 V 2
Input voltage range, SW (10 ns transient) SW -3 22 V 10 ns transient 2
Output voltage range, VREG5 VREG5 -0.3 6.5 V 2
Output voltage range, GND GND -0.3 0.3 V 2
Voltage from GND to thermal pad Vdiff -0.2 0.2 V 2
Electrostatic discharge, Human Body Model (HBM) 2 kV Human Body Model (HBM) 2
Electrostatic discharge, Charged Device Model (CDM) 500 V Charged Device Model (CDM) 2
Operating junction temperature TJ -40 150 °C 2
Storage temperature Tstg -55 150 °C 2
VIN supply input voltage range VIN 4.5 18 V 3
VBST VBST -0.1 24 V 3
VBST (10 ns transient) VBST -0.1 27 V 10 ns transient 3
VBST (vs SW) VBST (vs SW) -0.1 5.7 V 3
SS input voltage range SS -0.1 5.7 V 3
EN input voltage range EN -0.1 18 V 3
VFB input voltage range VFB -0.1 5.5 V 3
SW input voltage range SW -1.8 18 V 3
SW input voltage range (10 ns transient) SW -3 21 V 10 ns transient 3
GND voltage range GND -0.1 0.1 V 3
VREG5 output voltage range VREG5 -0.1 5.7 V 3
IVREG5 output current range IVREG5 0 10 mA 3
Operating free-air temperature TA -40 85 °C 3
Operating junction temperature TJ -40 150 °C 3
VIN operating non-switching supply current IVIN 800 1200 μA TA = 25°C, EN = 5 V, VFB = 0.8 V 3
VIN shutdown supply current IVINSDN 4.3 10 μA TA = 25°C, EN = 0 V 3
EN high-level input voltage VENH 1.6 V EN 3
EN low-level input voltage VENL 0.45 V EN 3
EN pin resistance to GND REN 220 440 880 kΩ VEN = 12 V 3
VFB threshold voltage VFBTH 749 765 781 mV TA = 25°C, VO = 1.05 V, continuous mode 3
VFB input current IVFB -0.1 0 0.1 μA VFB = 0.8 V, TA = 25°C 3
Current limit Iocl 3.5 4.2 5.7 A L out = 1.5 μH 3
Thermal shutdown threshold TSDN 165 °C 4
Thermal shutdown hysteresis TSDN 35 °C 4
SS charge current ISSC 4.2 6 7.8 μA VSS = 1 V 4
SS discharge current ISSD 0.1 0.2 mA VSS = 0.5 V 4
VREG5 output voltage VVREG5 5.5 V TA = 25°C, 6.0 V < VIN < 18 V, 0 < IVREG5 < 5 mA 3
VREG5 output current IVREG5 60 mA VIN = 6 V, VREG5 = 4.0 V, TA = 25°C 3
High side switch resistance RDS(on)h 100 mΩ 25°C, VBST - SW = 5.5 V 3
Low side switch resistance RDS(on)l 74 mΩ 25°C 3
On time tON 150 ns VIN = 12 V, VO = 1.05 V 4
Minimum off time tOFF(MIN) 260 ns TA = 25°C, VFB = 0.7 V 4
UVLO wake up VREG5 voltage UVLO 3.75 V 4
UVLO hysteresis VREG5 voltage UVLO 0.33 V 4
Thermal metric: junction-to-ambient thermal resistance θJA 42.1 °C/W DDA (8 pins) 2
Thermal metric: junction-to-case (top) thermal resistance θJCtop 50.9 °C/W DDA (8 pins) 2
Thermal metric: junction-to-board thermal resistance θJB 31.8 °C/W DDA (8 pins) 2
Thermal metric: junction-to-top characterization parameter ψJT 5 °C/W DDA (8 pins) 2
Thermal metric: junction-to-board characterization parameter ψJB 13.5 °C/W DDA (8 pins) 2
Thermal metric: junction-to-case (bottom) thermal resistance θJCbot 7.1 °C/W DDA (8 pins) 2

CAD (KiCad official)

  • Symbol: TPS54329DDAR
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: tps54329ddar-etched.step / tps54329ddar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54329ddar.step / tps54329ddar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 4e69e9b93fb82133, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF