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TPS54328DDAR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs tps54328ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers tps54328ddar: viewers · Ray 1mo ago
package.json tps54328ddar: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json tps54328ddar: specified limits as data (metadata.characteristics, 54 rows from the datasheet) · Ray 26d ago
README.md tps54328ddar: specified limits as data (metadata.characteristics, 54 rows from the datasheet) · Ray 26d ago
tps54328ddar-etched.fit.json tps54328ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps54328ddar-etched.glb tps54328ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps54328ddar-etched.step tps54328ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps54328ddar.glb Publish 0.1.0 · Ray 1mo ago
tps54328ddar.kicad_mod Publish 0.1.0 · Ray 1mo ago
tps54328ddar.kicad_sym Publish 0.1.0 · Ray 1mo ago
tps54328ddar.lbr Publish 0.1.0 · Ray 1mo ago
tps54328ddar.step Publish 0.1.0 · Ray 1mo ago

TPS54328DDAR

Texas Instruments · DC-DC Converters · SOIC-8-EP

TPS54328DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable input control, active high with logic high threshold of 1.6 V and low threshold of 0.45 V.
2 VFB input Converter feedback input with threshold voltage of 765 mV in continuous mode, connect to output voltage divider.
3 VREG5 power_out Regulated 5.5-V power output (5.2-5.7 V typical, 60 mA maximum) requiring 1-µF bypass capacitor to GND.
4 SS input Soft-start control input with 2-µA typical charge current (1.4-2.6 µA range) for external capacitor to GND.
5 GND power_in Ground and power return pin serving as single-point connection for sensitive SS and VFB signal returns.
6 SW output Switch node connection between high-side and low-side N-channel MOSFETs driving the output inductor.
7 VBST input Bootstrap supply input for high-side gate drive requiring 0.1-µF capacitor between VBST and SW, charged by internal diode from VREG5.
8 VIN power_in Input voltage supply pin with operating range of 4.5-18 V supplying main converter power.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating non-switching supply current IVIN 800 1200 µA TA = 25°C, EN = 5 V, VFB = 0.8 V 5
Shutdown supply current IVINSDN 1.8 10 µA TA = 25°C, EN = 0 V 5
VFB threshold voltage (continuous mode) VFBTH 749 765 781 mV TA = 25°C, VOUT = 1.05 V, continuous mode operation 5
VFB input current IVFB -0.1 0 0.1 µA VFB = 0.8 V, TA = 25°C 5
VREG5 output voltage VVREG5 5.2 5.5 5.7 V TA = 25°C, 6 V < VIN < 18 V, 0 < IVREG5 < 5 mA 5
Current limit IOCL 3.5 4.2 5.7 A LOUT = 1.5 µH, TA = –20ºC to 85ºC 5
UVLO threshold, wake-up VREG5 voltage UVLO 3.45 3.75 4.05 V Wake up VREG5 voltage 6
UVLO threshold, hysteresis VREG5 voltage UVLO 0.17 0.32 0.45 V Hysteresis VREG5 voltage 6
SS charge current ISSC 1.4 2 2.6 µA VSS = 0 V 5
SS discharge current ISSD 0.05 0.1 mA VSS = 0.5 V 5
Minimum off time tOFF(MIN) 260 310 ns TA = 25°C, VFB = 0.7 V 5
Input voltage (VIN, EN) VIN, EN -0.3 20 V 4
Input voltage (VBST) VBST -0.3 26 V 4
Input voltage (VBST, 10 ns transient) VBST -0.3 28 V 10 ns transient 4
Input voltage (VBST vs SW) VBST -0.3 6.5 V vs SW 4
Input voltage (VFB, SS) VFB, SS -0.3 6.5 V 4
Input voltage (SW) SW -2 20 V 4
Input voltage (SW, 10-ns transient) SW -3 22 V 10-ns transient 4
Output voltage (VREG5) VREG5 -0.3 6.5 V 4
Voltage (GND) GND -0.3 0.3 V 4
Voltage from GND to thermal pad Vdiff -0.2 0.2 V 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -55 150 °C 4
Supply input voltage VIN 4.5 18 V 4
Input voltage (VBST) VBST -0.1 24 V 4
Input voltage (VBST, 10-ns transient) VBST -0.1 27 V 10-ns transient 4
Input voltage (VBST vs SW) VBST(vs SW) -0.1 5.7 V vs SW 4
Input voltage (SS) SS -0.1 5.7 V 4
Input voltage (EN) EN -0.1 18 V 4
Input voltage (VFB) VFB -0.1 5.5 V 4
Input voltage (SW) SW -1.8 18 V 4
Input voltage (SW, 10-ns transient) SW -3 21 V 10-ns transient 4
Input voltage (GND) GND -0.1 0.1 V 4
Output voltage (VREG5) VOUT -0.1 5.7 V 4
Output current (IVREG5) IOUT 0 10 mA 4
Operating free-air temperature TA -40 85 °C 4
Operating junction temperature TJ -40 150 °C 4
EN high-level input voltage VENH 1.6 V EN 5
EN low-level input voltage VENL 0.45 V EN 5
VFB threshold voltage (Eco-mode) VFBTH 772 mV TA = 25°C, VOUT = 1.05 V, IOUT = 10 mA, Eco-mode operation 5
Line regulation VLN5 25 mV 6 V < VIN < 18 V, IVREG5 = 5 mA 5
Load regulation VLD5 100 mV 0 mA < IVREG5 < 5 mA 5
Output current IVREG5 60 mA VIN = 6 V, VVREG5 = 4 V, TA = 25°C 5
High-side switch resistance RDS(ON)H 100 mΩ TA = 25°C, VBST – SW = 5.5 V 5
Low-side switch resistance RDS(ON)L 70 mΩ TA = 25°C 5
Thermal shutdown threshold TSDN 165 °C Shutdown temperature (1) 5
Thermal shutdown hysteresis 30 °C Hysteresis (1) 5
ON time tON 150 ns VIN = 12 V, VOUT = 1.05 V 5
Junction-to-ambient thermal resistance (DDA) RθJA 42.1 °C/W DDA (HSOP) 8 pins 5
Junction-to-case (top) thermal resistance (DDA) RθJC(top) 50.9 °C/W DDA (HSOP) 8 pins 5
Junction-to-board thermal resistance (DDA) RθJB 31.8 °C/W DDA (HSOP) 8 pins 5
Junction-to-top characterization parameter (DDA) ψJT 5 °C/W DDA (HSOP) 8 pins 5
Junction-to-board characterization parameter (DDA) ψJB 13.5 °C/W DDA (HSOP) 8 pins 5
Junction-to-case (bottom) thermal resistance (DDA) RθJC(bot) 7.1 °C/W DDA (HSOP) 8 pins 5

CAD (KiCad official)

  • Symbol: TPS54328DDAR
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: tps54328ddar-etched.step / tps54328ddar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54328ddar.step / tps54328ddar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 54b1b4f4006b0b79, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF