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TPS54290PWPR

Texas Instruments · DC-DC Converters · HTSSOP-16-EP

TPS54290PWPR from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PVDD1 power_in Power input to the Output1 high-side MOSFET only; it must be locally bypassed to PGND1 with a low-ESR ceramic capacitor of 10 µF or greater, and may be tied externally to PVDD2.
2 BOOT1 input Input supply to the Output1 high-side gate driver; connect a 22-nF to 68-nF capacitor from this pin to SW1, optionally with a 2 Ω to 5 Ω series resistor to slow the turn-on.
3 SW1 output Source (switching) output for the Output1 PWM.
4 PGND1 power_in Power ground for Output1, separated from GND to keep switching noise out of the internal logic circuits.
5 EN1 input Active-low enable for Output1: above 1.5 V disables Output1, below 0.9 V enables it and starts soft start, and it is pulled to PVDD2 by an internal current source if left floating; connect to GND to bypass the enable function.
6 EN2 input Active-low enable for Output2: above 1.5 V disables Output2, below 0.9 V enables it and starts soft start, and it is pulled to PVDD2 by an internal current source if left floating; connect to GND to bypass the enable function.
7 FB1 input Output1 voltage feedback; the internal gM error amplifier regulates this pin to the internal 0.8-V reference, set by an external resistor divider from VOUT1.
8 COMP1 output Output of the Output1 transconductance (gM) error amplifier; an R-C compensation network is connected from this pin to GND.
9 COMP2 output Output of the Output2 transconductance (gM) error amplifier; an R-C compensation network is connected from this pin to GND.
10 FB2 input Output2 voltage feedback; the internal gM error amplifier regulates this pin to the internal 0.8-V reference, set by an external resistor divider from VOUT2.
11 GND power_in Analog ground pin for the device.
12 BP power_out Regulated voltage that charges the bootstrap capacitors; bypass to GND with a low-ESR 4.7-µF ceramic capacitor (10 µF preferred).
13 PGND2 power_in Power ground for Output2, separated from GND to keep switching noise out of the internal logic circuits.
14 SW2 output Source (switching) output for the Output2 PWM.
15 BOOT2 input Input supply to the Output2 high-side gate driver; connect a 22-nF to 68-nF capacitor from this pin to SW2, optionally with a 2 Ω to 5 Ω series resistor to slow the turn-on.
16 PVDD2 power_in Supplies the control circuitry, the EN1/EN2 pull-ups and the Output2 high-side MOSFET; it must be bypassed to PGND2 with at least 10 µF low-ESR ceramic, and UVLO enables the device when PVDD2 exceeds 4.2 V.
17 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16-EP
Category Power Management (PMIC)
Pins 17

CAD (KiCad official)

  • Symbol: TPS54290PWPR
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: tps54290pwpr-etched.step / tps54290pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54290pwpr.step / tps54290pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 9b88a4b17358c967, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF