component
TPS54233DR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownTPS54233DR
Texas Instruments · DC-DC Converters · SOIC-8
TPS54233DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap supply node; connect 0.1 μF ceramic capacitor between BOOT and PH; integrated boot regulator sources this node; MOSFET disabled if BOOT-PH voltage falls below 2.1 V typical; rated 0-38 V absolute maximum. |
| 2 | VIN | power_in | Input power supply; accepts regulated DC voltage from 3.5 V to 28 V; rated -0.3 V to 30 V absolute maximum; internal supply bias and high-side MOSFET gate driver powered from this pin. |
| 3 | EN | input | Enable control input; float to enable converter or pull below 1.25 V threshold to disable; internal pull-up current source (1-3 μA) available for external UVLO threshold divider programming; rated -0.3 V to 6 V absolute maximum. |
| 4 | SS | passive | Slow start network node; external capacitor (1-27 nF recommended) connects to ground and charges from 2 μA current source to set output voltage rise time from 1 ms to 10 ms; rated -0.3 V to 3 V absolute maximum; 200 μA sink current specified. |
| 5 | VSENSE | input | Inverting input to transconductance error amplifier (92 μA/V gain, 800 V/V DC gain); connect output voltage divider tap for feedback regulation and closed-loop control; rated -0.3 V to 3 V absolute maximum; 10 μA sink current specified. |
| 6 | COMP | output | Error amplifier output and PWM comparator input; attach frequency compensation network (series R and C to ground) to set loop crossover frequency and phase margin; rated -0.3 V to 3 V absolute maximum; source/sink current ±7 μA at 1 V nominal; maximum clamp limits peak inductor current. |
| 7 | GND | power_in | Ground reference; provides return path for all power supplies and signal circuits; fused lead frame improves thermal dissipation; connect to ground plane via multiple vias for heat removal. |
| 8 | PH | output | Switching node output of integrated high-side MOSFET (80 mΩ typical on-resistance); voltage swings from 0 V to BOOT-PH voltage level during switching; connect to output inductor and catch diode cathode to complete buck converter power stage; rated -0.6 V to 30 V absolute maximum; source current 6 A specified. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPS54233DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tps54233dr-etched.step/tps54233dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54233dr.step/tps54233dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
82b6671a411fda8e, retrieved 2026-09-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).