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TPS54225PWPR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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tps54225pwpr: specified limits as data (metadata.characteristics, 59 rows from the datasheet)
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TPS54225PWPR
Texas Instruments · DC-DC Converters · HTSSOP-14
TPS54225PWPR from Texas Instruments, in a HTSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VO | input | Connect to output of converter; this pin is used for On-Time Adjustment. |
| 2 | VFB | input | Converter feedback input; connect with feedback resistor divider. |
| 3 | VREG5 | power_out | 5.5 V internal power supply output; a capacitor (typical 1 uF) should be connected to GND. |
| 4 | SS | passive | Soft-start control pin; an external capacitor should be connected to GND to set the slow-start time. |
| 5 | GND | power_in | Signal ground pin. |
| 6 | PG | output | Open drain power good output. |
| 7 | EN | input | Enable control input. |
| 8 | PGND1 | power_in | Ground return for low-side MOSFET; also serves as input of a current comparator, and should be connected strongly together with PGND near the IC. |
| 9 | PGND2 | power_in | Ground return for low-side MOSFET; also serves as input of a current comparator, and should be connected strongly together with PGND near the IC. |
| 10 | SW1 | output | Switch node connection between high-side NFET and low-side NFET; also serves as an input to a current comparator. |
| 11 | SW2 | output | Switch node connection between high-side NFET and low-side NFET; also serves as an input to a current comparator. |
| 12 | VBST | power_in | Supply input for the high-side NFET gate driver (boost terminal); a capacitor should be connected from this pin to the respective SW1, SW2 terminals, and an internal PN diode connects VREG5 to this pin. |
| 13 | VIN | power_in | Power input, connected to the high-side NFET drain. |
| 14 | VCC | power_in | Supply input for the 5 V internal linear regulator that powers the control circuitry. |
| 15 | PowerPAD | power_in | Thermal pad of the package (back side); must be soldered to achieve appropriate dissipation and should be connected to PGND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-14 |
| Category | Power Management (PMIC) |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply input voltage range | VCC | 4.5 | 18 | V | 3 | ||
| Power input voltage range | VIN | 2 | 18 | V | 3 | ||
| Input voltage range (boost terminal) | VBST | -0.1 | 24 | V | 3 | ||
| Input voltage range (boost vs SW1, SW2) | VBST (vs SW1, SW2) | -0.1 | 5.7 | V | 3 | ||
| Input voltage range (soft start, power good) | SS, PG | -0.1 | 5.7 | V | 3 | ||
| Input voltage range (enable) | EN | -0.1 | 18 | V | 3 | ||
| Input voltage range (output, feedback) | VO, VFB | -0.1 | 5.5 | V | 3 | ||
| Switch node voltage range | SW1, SW2 | -1.8 | 18 | V | 3 | ||
| Switch node voltage range (10 ns transient) | SW1, SW2 | -3 | 18 | V | 10 ns transient | 3 | |
| Ground voltage range (power ground) | PGND1, PGND2 | -0.1 | 0.1 | V | 3 | ||
| Output voltage range (VREG5) | VREG5 | -0.1 | 5.7 | V | 3 | ||
| Output current range | IO | 0 | 10 | mA | IVREG5 | 3 | |
| Operating free-air temperature | TA | -40 | 85 | °C | 3 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 3 | ||
| Input voltage range (VIN, VCC, EN) | VIN, VCC, EN | -0.3 | 20 | V | 2 | ||
| Input voltage range (VBST) | VBST | -0.3 | 26 | V | 2 | ||
| Input voltage range (VBST vs SW1, SW2) | VBST (vs SW1, SW2) | -0.3 | 6.5 | V | 2 | ||
| Input voltage range (VFB, VO, SS, PG) | VFB, VO, SS, PG | -0.3 | 6.5 | V | 2 | ||
| Switch node voltage range (SW1, SW2) | SW1, SW2 | -2 | 20 | V | 2 | ||
| Switch node voltage range (10 ns transient) | SW1, SW2 | -3 | 20 | V | 10 ns transient | 2 | |
| Output voltage range (VREG5) | VREG5 | -0.3 | 6.5 | V | 2 | ||
| Ground voltage range (PGND1, PGND2) | PGND1, PGND2 | -0.3 | 0.3 | V | 2 | ||
| Voltage from GND to POWERPAD | Vdiff | -0.2 | 0.2 | V | 2 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 2 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 2 | ||
| Operating non-switching supply current | IVCC | 800 | 1200 | μA | VCC, VIN = 12 V; TA = 25°C, EN = 5 V, VFB = 0.8 V | 3 | |
| Shutdown supply current | IVCCSDN | 1.8 | 10 | μA | VCC, VIN = 12 V; TA = 25°C, EN = 0 V | 3 | |
| EN high-level input voltage | VENH | 2 | V | VCC, VIN = 12 V | 3 | ||
| EN low-level input voltage | VENL | 0.4 | V | VCC, VIN = 12 V | 3 | ||
| VFB threshold voltage | VFB | 757 | 765 | 773 | mV | VCC, VIN = 12 V; TA = 25°C, VO = 1.05 V | 3 |
| VFB threshold voltage | VFB | 753 | 777 | mV | VCC, VIN = 12 V; TA = 0°C to 85°C, VO = 1.05 V | 3 | |
| VFB threshold voltage | VFB | 751 | 779 | mV | VCC, VIN = 12 V; TA = -40°C to 85°C, VO = 1.05 V | 3 | |
| VFB input current | IVFB | -0.1 | 0 | 0.1 | μA | VCC, VIN = 12 V; VFB = 0.8 V, TA = 25°C | 3 |
| VO discharge resistance | RDischg | 50 | 100 | Ω | VCC, VIN = 12 V; EN = 0 V, VO = 0.5 V, TA = 25°C | 3 | |
| VREG5 output voltage | VREG5 | 5.3 | 5.5 | 5.7 | V | VCC, VIN = 12 V; TA = 25°C, 6 V < VCC < 18 V, 0 < IVREG5 < 5 mA | 3 |
| Current limit | Iocl | 2.5 | 3.1 | 4.5 | A | VCC, VIN = 12 V; LOUT = 2.2µH | 3 |
| Minimum off time | tOFF(MIN) | 260 | 310 | ns | VCC, VIN = 12 V; TA = 25°C, VFB = 0.7 V | 4 | |
| Soft-start charge current | ISSC | 1.4 | 2 | 2.6 | μA | VCC, VIN = 12 V; VSS = 0 V | 4 |
| Soft-start discharge current | ISSD | 0.1 | 0.2 | mA | VCC, VIN = 12 V; VSS = 0.5 V | 4 | |
| Power good threshold (VFB rising, good) | VTHPG | 85 | 90 | 95 | % | VCC, VIN = 12 V; VFB rising (good) | 4 |
| Power good sink current | IPG | 2.5 | 5 | mA | VCC, VIN = 12 V; PG = 0.5 V | 4 | |
| Output OVP trip threshold | VOVP | 115 | 120 | 125 | % | VCC, VIN = 12 V; OVP detect | 4 |
| Output UVP trip threshold | VUVP | 65 | 70 | 75 | % | VCC, VIN = 12 V; UVP detect | 4 |
| Wake up VREG5 voltage (UVLO threshold) | UVLO | 3.55 | 3.8 | 4.05 | V | VCC, VIN = 12 V; Wake up VREG5 voltage | 4 |
| Hysteresis VREG5 voltage (UVLO) | UVLO | 0.23 | 0.35 | 0.47 | V | VCC, VIN = 12 V; Hysteresis VREG5 voltage | 4 |
| Output current | IVREG5 | 70 | mA | VCC, VIN = 12 V; VCC = 6 V, VREG5 = 4 V, TA = 25°C | 3 | ||
| Line regulation | VLN5 | 20 | mV | VCC, VIN = 12 V; 6 V < VCC < 18 V, IVREG5 = 5 mA | 3 | ||
| Load regulation | VLD5 | 100 | mV | VCC, VIN = 12 V; 0 mA < IVREG5 < 5 mA | 3 | ||
| High side switch resistance | RDS(on)h | 160 | mΩ | VCC, VIN = 12 V; 25°C, VBST - SW1, SW2 = 5.5 V | 3 | ||
| Low side switch resistance | RDS(on)l | 110 | mΩ | VCC, VIN = 12 V; 25°C | 3 | ||
| Thermal shutdown threshold | TSDN | 150 | °C | VCC, VIN = 12 V | 3 | ||
| Thermal shutdown hysteresis | TSDN | 25 | °C | VCC, VIN = 12 V | 3 | ||
| On time | tON | 145 | ns | VCC, VIN = 12 V; VIN = 12 V, VO = 1.05 V | 4 | ||
| Junction-to-ambient thermal resistance | θJA | 55.6 | °C/W | PWP package, 14 pins | 2 | ||
| Junction-to-case (top) thermal resistance | θJCtop | 51.3 | °C/W | PWP package, 14 pins | 2 | ||
| Junction-to-board thermal resistance | θJB | 26.4 | °C/W | PWP package, 14 pins | 2 | ||
| Junction-to-top characterization parameter | ψJT | 1.8 | °C/W | PWP package, 14 pins | 2 | ||
| Junction-to-board characterization parameter | ψJB | 20.6 | °C/W | PWP package, 14 pins | 2 | ||
| Junction-to-case (bottom) thermal resistance | θJCbot | 4.3 | °C/W | PWP package, 14 pins | 2 |
CAD (KiCad official)
- Symbol:
TPS54225PWPR - Footprint:
Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
tps54225pwpr-etched.step/tps54225pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54225pwpr.step/tps54225pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
3c3ac317d4ab1b65, retrieved 2026-09-24, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS54225PWPR
**Texas Instruments** · DC-DC Converters · HTSSOP-14
TPS54225PWPR from Texas Instruments, in a HTSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VO | input | Connect to output of converter; this pin is used for On-Time Adjustment. |
| 2 | VFB | input | Converter feedback input; connect with feedback resistor divider. |
| 3 | VREG5 | power_out | 5.5 V internal power supply output; a capacitor (typical 1 uF) should be connected to GND. |
| 4 | SS | passive | Soft-start control pin; an external capacitor should be connected to GND to set the slow-start time. |
| 5 | GND | power_in | Signal ground pin. |
| 6 | PG | output | Open drain power good output. |
| 7 | EN | input | Enable control input. |
| 8 | PGND1 | power_in | Ground return for low-side MOSFET; also serves as input of a current comparator, and should be connected strongly together with PGND near the IC. |
| 9 | PGND2 | power_in | Ground return for low-side MOSFET; also serves as input of a current comparator, and should be connected strongly together with PGND near the IC. |
| 10 | SW1 | output | Switch node connection between high-side NFET and low-side NFET; also serves as an input to a current comparator. |
| 11 | SW2 | output | Switch node connection between high-side NFET and low-side NFET; also serves as an input to a current comparator. |
| 12 | VBST | power_in | Supply input for the high-side NFET gate driver (boost terminal); a capacitor should be connected from this pin to the respective SW1, SW2 terminals, and an internal PN diode connects VREG5 to this pin. |
| 13 | VIN | power_in | Power input, connected to the high-side NFET drain. |
| 14 | VCC | power_in | Supply input for the 5 V internal linear regulator that powers the control circuitry. |
| 15 | PowerPAD | power_in | Thermal pad of the package (back side); must be soldered to achieve appropriate dissipation and should be connected to PGND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-14 |
| Category | Power Management (PMIC) |
| Pins | 15 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply input voltage range | VCC | 4.5 | | 18 | V | | 3 |
| Power input voltage range | VIN | 2 | | 18 | V | | 3 |
| Input voltage range (boost terminal) | VBST | -0.1 | | 24 | V | | 3 |
| Input voltage range (boost vs SW1, SW2) | VBST (vs SW1, SW2) | -0.1 | | 5.7 | V | | 3 |
| Input voltage range (soft start, power good) | SS, PG | -0.1 | | 5.7 | V | | 3 |
| Input voltage range (enable) | EN | -0.1 | | 18 | V | | 3 |
| Input voltage range (output, feedback) | VO, VFB | -0.1 | | 5.5 | V | | 3 |
| Switch node voltage range | SW1, SW2 | -1.8 | | 18 | V | | 3 |
| Switch node voltage range (10 ns transient) | SW1, SW2 | -3 | | 18 | V | 10 ns transient | 3 |
| Ground voltage range (power ground) | PGND1, PGND2 | -0.1 | | 0.1 | V | | 3 |
| Output voltage range (VREG5) | VREG5 | -0.1 | | 5.7 | V | | 3 |
| Output current range | IO | 0 | | 10 | mA | IVREG5 | 3 |
| Operating free-air temperature | TA | -40 | | 85 | °C | | 3 |
| Operating junction temperature | TJ | -40 | | 125 | °C | | 3 |
| Input voltage range (VIN, VCC, EN) | VIN, VCC, EN | -0.3 | | 20 | V | | 2 |
| Input voltage range (VBST) | VBST | -0.3 | | 26 | V | | 2 |
| Input voltage range (VBST vs SW1, SW2) | VBST (vs SW1, SW2) | -0.3 | | 6.5 | V | | 2 |
| Input voltage range (VFB, VO, SS, PG) | VFB, VO, SS, PG | -0.3 | | 6.5 | V | | 2 |
| Switch node voltage range (SW1, SW2) | SW1, SW2 | -2 | | 20 | V | | 2 |
| Switch node voltage range (10 ns transient) | SW1, SW2 | -3 | | 20 | V | 10 ns transient | 2 |
| Output voltage range (VREG5) | VREG5 | -0.3 | | 6.5 | V | | 2 |
| Ground voltage range (PGND1, PGND2) | PGND1, PGND2 | -0.3 | | 0.3 | V | | 2 |
| Voltage from GND to POWERPAD | Vdiff | -0.2 | | 0.2 | V | | 2 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 2 |
| Storage temperature | Tstg | -55 | | 150 | °C | | 2 |
| Operating non-switching supply current | IVCC | | 800 | 1200 | μA | VCC, VIN = 12 V; TA = 25°C, EN = 5 V, VFB = 0.8 V | 3 |
| Shutdown supply current | IVCCSDN | | 1.8 | 10 | μA | VCC, VIN = 12 V; TA = 25°C, EN = 0 V | 3 |
| EN high-level input voltage | VENH | 2 | | | V | VCC, VIN = 12 V | 3 |
| EN low-level input voltage | VENL | | | 0.4 | V | VCC, VIN = 12 V | 3 |
| VFB threshold voltage | VFB | 757 | 765 | 773 | mV | VCC, VIN = 12 V; TA = 25°C, VO = 1.05 V | 3 |
| VFB threshold voltage | VFB | 753 | | 777 | mV | VCC, VIN = 12 V; TA = 0°C to 85°C, VO = 1.05 V | 3 |
| VFB threshold voltage | VFB | 751 | | 779 | mV | VCC, VIN = 12 V; TA = -40°C to 85°C, VO = 1.05 V | 3 |
| VFB input current | IVFB | -0.1 | 0 | 0.1 | μA | VCC, VIN = 12 V; VFB = 0.8 V, TA = 25°C | 3 |
| VO discharge resistance | RDischg | | 50 | 100 | Ω | VCC, VIN = 12 V; EN = 0 V, VO = 0.5 V, TA = 25°C | 3 |
| VREG5 output voltage | VREG5 | 5.3 | 5.5 | 5.7 | V | VCC, VIN = 12 V; TA = 25°C, 6 V < VCC < 18 V, 0 < IVREG5 < 5 mA | 3 |
| Current limit | Iocl | 2.5 | 3.1 | 4.5 | A | VCC, VIN = 12 V; LOUT = 2.2µH | 3 |
| Minimum off time | tOFF(MIN) | | 260 | 310 | ns | VCC, VIN = 12 V; TA = 25°C, VFB = 0.7 V | 4 |
| Soft-start charge current | ISSC | 1.4 | 2 | 2.6 | μA | VCC, VIN = 12 V; VSS = 0 V | 4 |
| Soft-start discharge current | ISSD | | 0.1 | 0.2 | mA | VCC, VIN = 12 V; VSS = 0.5 V | 4 |
| Power good threshold (VFB rising, good) | VTHPG | 85 | 90 | 95 | % | VCC, VIN = 12 V; VFB rising (good) | 4 |
| Power good sink current | IPG | 2.5 | | 5 | mA | VCC, VIN = 12 V; PG = 0.5 V | 4 |
| Output OVP trip threshold | VOVP | 115 | 120 | 125 | % | VCC, VIN = 12 V; OVP detect | 4 |
| Output UVP trip threshold | VUVP | 65 | 70 | 75 | % | VCC, VIN = 12 V; UVP detect | 4 |
| Wake up VREG5 voltage (UVLO threshold) | UVLO | 3.55 | 3.8 | 4.05 | V | VCC, VIN = 12 V; Wake up VREG5 voltage | 4 |
| Hysteresis VREG5 voltage (UVLO) | UVLO | 0.23 | 0.35 | 0.47 | V | VCC, VIN = 12 V; Hysteresis VREG5 voltage | 4 |
| Output current | IVREG5 | | 70 | | mA | VCC, VIN = 12 V; VCC = 6 V, VREG5 = 4 V, TA = 25°C | 3 |
| Line regulation | VLN5 | | 20 | | mV | VCC, VIN = 12 V; 6 V < VCC < 18 V, IVREG5 = 5 mA | 3 |
| Load regulation | VLD5 | | 100 | | mV | VCC, VIN = 12 V; 0 mA < IVREG5 < 5 mA | 3 |
| High side switch resistance | RDS(on)h | | 160 | | mΩ | VCC, VIN = 12 V; 25°C, VBST - SW1, SW2 = 5.5 V | 3 |
| Low side switch resistance | RDS(on)l | | 110 | | mΩ | VCC, VIN = 12 V; 25°C | 3 |
| Thermal shutdown threshold | TSDN | | 150 | | °C | VCC, VIN = 12 V | 3 |
| Thermal shutdown hysteresis | TSDN | | 25 | | °C | VCC, VIN = 12 V | 3 |
| On time | tON | | 145 | | ns | VCC, VIN = 12 V; VIN = 12 V, VO = 1.05 V | 4 |
| Junction-to-ambient thermal resistance | θJA | | 55.6 | | °C/W | PWP package, 14 pins | 2 |
| Junction-to-case (top) thermal resistance | θJCtop | | 51.3 | | °C/W | PWP package, 14 pins | 2 |
| Junction-to-board thermal resistance | θJB | | 26.4 | | °C/W | PWP package, 14 pins | 2 |
| Junction-to-top characterization parameter | ψJT | | 1.8 | | °C/W | PWP package, 14 pins | 2 |
| Junction-to-board characterization parameter | ψJB | | 20.6 | | °C/W | PWP package, 14 pins | 2 |
| Junction-to-case (bottom) thermal resistance | θJCbot | | 4.3 | | °C/W | PWP package, 14 pins | 2 |
## CAD (KiCad official)
- Symbol: `TPS54225PWPR`
- Footprint: `Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm`
- 3D model: HTSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `tps54225pwpr-etched.step` / `tps54225pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54225pwpr.step` / `tps54225pwpr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54225) (29 pp, sha256 `3c3ac317d4ab1b65`, retrieved 2026-09-24, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps54225pwpr-datasheet.pdf)