component

TPS5420DR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentpmictps5420dr
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs tps5420dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json tps5420dr: specified limits as data (metadata.characteristics, 39 rows from the datasheet) · Ray
README.md tps5420dr: specified limits as data (metadata.characteristics, 39 rows from the datasheet) · Ray
tps5420dr-etched.fit.json tps5420dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tps5420dr-etched.glb tps5420dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tps5420dr-etched.step tps5420dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tps5420dr.glb Publish 0.1.0 · Ray
tps5420dr.kicad_mod Publish 0.1.0 · Ray
tps5420dr.kicad_sym Publish 0.1.0 · Ray
tps5420dr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
tps5420dr.step Publish 0.1.0 · Ray

TPS5420DR

Texas Instruments · DC-DC Converters · SOIC-8

TPS5420DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT passive Boost capacitor pin for the high-side FET gate driver. Connect a 0.01µF low-ESR ceramic capacitor from BOOT to PH to provide gate drive above VIN.
2 NC unconnected Not connected internally.
3 NC unconnected Not connected internally.
4 VSENSE input Feedback voltage input for the regulator error amplifier. Connect to the output voltage divider; regulates to VFB = 1.221V typical (adjustable output down to 1.22V).
5 ENA input Active-high enable / on-off control. Below 0.5V the device stops switching; above 1.3V the device starts switching. Internally pulled up via a 1.5MΩ resistor so the pin may be left floating; do not connect through a resistor to ground.
6 GND power_in Device ground return.
7 VIN power_in Input supply voltage, 5.5V to 36V (40V absolute max). Bypass with a high-quality low-ESR ceramic capacitor placed within 1mm of VIN and GND.
8 PH power_out Phase / switch node - source of the high-side power MOSFET. Connect to the external inductor and catch (Schottky) diode. Delivers up to 2A continuous (3A peak); on-resistance 110mΩ typical.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • TPS5420DR
  • TPS5420DRD

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN to GND -0.3 40 V 4
Input voltage ENA to GND -0.3 7 V 4
Input voltage VSENSE to GND -0.3 3 V 4
Output voltage BOOT to PH -0.3 6 V 4
Output voltage PH to GND -0.6 40 V Steady-state 4
Output voltage BOOT to GND -0.3 V 4
Output voltage PH to GND -1.2 V transient < 10ns 4
PH leakage current 10 µA 4
Operating virtual junction temperature TJ TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD Human-body model (HBM) V(ESD) -2000 2000 V Per ANSI/ESDA/JEDEC JS-001 4
ESD Charged-device model (CDM) V(ESD) -750 750 V Per JEDEC JESD22-C101 4
Input voltage range 5.5 36 V 4
Operating junction temperature TJ -40 125 °C 4
VIN quiescent current IQ(VIN) 2 4.4 mA Non-switching, VSENSE = 2V, PH pin open 5
VIN shutdown supply current ISD(VIN) 15 50 µA Shutdown, ENA = 0V 5
VIN UVLO rising threshold VINUVLO(R) 5.3 5.5 V VVIN rising 5
FB voltage VFB 1.202 1.221 1.239 V TJ = 25°C 5
FB voltage VFB 1.196 1.221 1.245 V TJ = –40°C to 125°C 5
Switching frequency fSW 400 500 600 kHz 5
Minimum ON pulse width tON(min) 150 200 ns 5
Maximum duty cycle DMAX 85 89 % fSW = 500kHz 5
Internal slow-start time (0 to 100%) tSS 6.6 8 10 ms 5
High-side peak current limit IHS(OC) 3 4 5 A 5
Hiccup time before re-start 13 16 20 ms 5
High-side MOSFET on-resistance RDSON(HS) 100 230 mΩ VIN = 12V, VBOOT-SW = 4.5V 5
Thermal shutdown threshold TJ(SD) 135 162 °C Temperature rising 5
VIN UVLO hysteresis VINUVLO(H) 0.35 V 5
ENA voltage rising threshold VEN(R) 1.3 V 5
ENA voltage falling threshold VEN(F) 0.5 V 5
ENA voltage hysteresis VEN(H) 325 mV 5
High-side MOSFET on-resistance RDSON(HS) 125 mΩ VIN = 5.5V, VBOOT-SW = 4.0V 5
Thermal shutdown hysteresis TJ(HYS) 14 °C 5
Junction-to-ambient thermal resistance (Custom Board) RθJA 75 °C/W Custom board 4
Junction-to-ambient thermal resistance (JESD 51-7) RθJA 106 °C/W JESD 51-7, 4-layer JEDEC board 4
Junction-to-case (top) thermal resistance RθJC(top) 54 °C/W 4
Junction-to-board thermal resistance RθJB 55 °C/W 4
Junction-to-top characterization parameter ψJT 15 °C/W 4
Junction-to-board characterization parameter ψJB 56 °C/W 4

CAD (KiCad official)

  • Symbol: TPS5420DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tps5420dr-etched.step / tps5420dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps5420dr.step / tps5420dr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tps5420dr.step 122 KB You want the bare part, or you mark your own boards.
tps5420dr-etched.step 2.0 MB You want the part with TPS5420DR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 506 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 cd667e69b40fa9c0, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF