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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS53647RTAR

Texas Instruments · AC-DC Controllers And Regulators · WQFN-40-EP(6x6)

TPS53647RTAR from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OCL-R	input	Voltage divider to VREF pin; resistor (ROCL-R) to GND sets per-phase overcurrent limit level and selects ramp amplitude from four options.
2	IMON	output	Analog current monitor output; resistor to GND generates output voltage proportional to sum of phase currents at 5 mV/A scaling.
3	CSP1	input	Positive current sense input for phase 1; connect to IOUT pin of TI smart power stages; tie CSP1 to V3R3 to disable phase 1.
4	CSP2	input	Positive current sense input for phase 2; connect to IOUT pin of TI smart power stages; tie CSP2 to V3R3 to disable phase 2.
5	CSP3	input	Positive current sense input for phase 3; connect to IOUT pin of TI smart power stages; tie CSP3 to V3R3 to disable phase 3.
6	CSP4	input	Positive current sense input for phase 4; connect to IOUT pin of TI smart power stages; tie CSP4 to V3R3 to disable phase 4.
7	NC	unconnected	No internal connection; leave the pin open or pull up to V3R3 pin.
8	NC	unconnected	No connection.
9	VSP	input	Positive input of the remote voltage sense amplifier; connect directly to the output voltage being regulated.
10	VSN	input	Negative input of the remote voltage sense amplifier; connect directly to GND of the load for accurate output voltage sensing.
11	COMP	output	Output of the gM error amplifier; resistors and capacitors between this pin and VREF pin set the feedback compensation network.
12	ISUM	output	Current sum output; resistor (RISUM) to VREF pin determines the load-line droop voltage as function of output current.
13	VREF	power_out	1.7-V, 500-µA, LDO reference voltage output; bypass to GND with 0.33 µF capacitor; connect to REFIN of TI power stages as current-sense reference.
14	V3R3	power_out	3.3-V LDO output from V5; bypass to GND with 1-µF or larger ceramic capacitor; powers internal digital circuits and provides pull-up source for open-drain outputs.
15	V5	power_in	5-V power input; bypass to GND with 1-µF or larger ceramic capacitor; supplies all internal analog circuits; rated 4.5 V to 5.5 V operating range.
16	VIN	power_in	Input voltage supply; also used for input voltage sensing for on-time control and UVLO detection; rated 4.5 V to 17 V operating range.
17	GND	power_in	Ground pin (IC ground); primary ground reference for all internal circuits.
18	VR_RDY	tri_state	Power good open-drain output; typically pulled up to V3R3 through 3-kΩ or larger resistor; asserts high when output voltage in regulation within UVP/OVP thresholds.
19	VR_HOT	tri_state	Thermal flag open-drain output, active low; typically pulled up to V3R3 through 3-kΩ or larger resistor; asserts low when sensed temperature exceeds 110°C default warning threshold.
20	GND	power_in	Ground pin; connect to GND (noted as not IC ground pin in schematic context).
21	RESET	input	Reset pin; if low for more than 1000 ns, controller pulls output voltage to VBOOT level for adaptive voltage scaling reset function.
22	GND	power_in	Ground pin; connect to GND (noted as not IC ground pin in schematic context).
23	ENABLE	input	VR enable control pin; 1-V I/O level with 100-ns debounce; high enables output, low disables output and enters standby mode.
24	PMB_CLK	input	I2C PMBus clock input; 3.3-V and 1.8-V logic level compatible; part of PMBus communication protocol supporting 100 kHz and 400 kHz bus speeds.
25	PMB_ALERT	tri_state	I2C PMBus interrupt line, open-drain output; 3.3-V and 1.8-V logic level compatible; asserts low to alert master of fault condition on PMBus.
26	PMB_DIO	bidirectional	I2C PMBus digital I/O line; 3.3-V and 1.8-V logic level compatible; used for bidirectional PMBus data transmission and communication protocol.
27	VR_FAULT	tri_state	VR fault indicator, open-drain output, active low; asserts for input overcurrent, over-temperature, output overvoltage, and power stage faults; typically pulled up to V3R3 or left floating if not used.
28	ADDR-TRISE	input	Voltage divider to VREF pin; resistor (RADDR-TRISE) to GND sets 3 bits for soft-start slew rate and boot voltage LSB; voltage level sets 4 bits of PMBus address (16 possible).
29	SLEW-MODE	input	Voltage divider to VREF pin; resistor (RSLEW-MODE) to GND selects output voltage change slew rate (0.34 to 2.74 mV/µs); voltage sets 4-bit operation mode bits for DAC mode, phase interleaving, dynamic phase shedding, and zero load-line.
30	O-USR	input	Voltage divider to VREF pin; resistor (RO-USR) to GND selects one of 7 OSR (overshoot reduction) thresholds or OFF; voltage sets one of 7 USR (undershoot reduction) levels or OFF for transient improvement.
31	VBOOT	input	Voltage divider to VREF pin; resistor (RVBOOT) to GND sets bits 3:1 of boot voltage VID; voltage sets bits 7:4, total 7 bits set output voltage at startup from 0.5 V to 2.5 V.
32	F-IMAX	input	Voltage divider to VREF pin; resistor (RF-IMAX) to GND sets switching frequency from 300 kHz to 1 MHz; voltage sets maximum operating current (IMAX) with 8-bit A/D where IMAX = (VF-IMAX/VREF) × 256 - 0.5.
33	NC	unconnected	No connection.
34	NC	unconnected	No connection.
35	PWM4	output	PWM signal output for phase 4; 3.3-V logic output; high turns on high-side MOSFET, low turns on low-side MOSFET, tri-state (1.7 V) for both MOSFETs off.
36	PWM3	output	PWM signal output for phase 3; 3.3-V logic output; high turns on high-side MOSFET, low turns on low-side MOSFET, tri-state (1.7 V) for both MOSFETs off.
37	PWM2	output	PWM signal output for phase 2; 3.3-V logic output; high turns on high-side MOSFET, low turns on low-side MOSFET, tri-state (1.7 V) for both MOSFETs off.
38	PWM1	output	PWM signal output for phase 1; 3.3-V logic output; high turns on high-side MOSFET, low turns on low-side MOSFET, tri-state (1.7 V) for both MOSFETs off.
39	SKIP-NVM	output	SKIP-NVM output pin; resistor (RSKIP-NVM) to GND sets pinstrap or NVM configuration mode; can connect to FCCM pin of TI power stages for SKIP or FCCM operation mode selection.
40	TSEN	input	Temperature sense input; connect to TAO/FAULT pin of TI smart power stages to sense highest die temperature and power stage fault signals; 0°C to 127.9°C measurement range.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-40-EP(6x6)
Category	Power Management (PMIC)
Pins	41

CAD (KiCad official)

Symbol: TPS53647RTAR
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
3D model files: tps53647rtar-etched.step / tps53647rtar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps53647rtar.step / tps53647rtar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (123 pp, sha256 2a0c7fc1d7dab847, retrieved 2026-09-27, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF