# TPS51222RTVR

**Texas Instruments** · DC-DC Converters · WQFN-32-EP(5x5)

TPS51222RTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DRVH1 | output | High-side MOSFET gate driver output for channel 1, rated source 1.7 Ω and sink 1.0 Ω, SW-node referenced floating driver whose drive voltage is VBST to SW. |
| 2 | V5SW | input | Switchover supply input for VREG5; switchover is enabled when EN1 is high, PGOOD1 indicates good and V5SW is above 4.8 V, and VREG5 then sits approximately at the V5SW voltage. |
| 3 | RF | bidirectional | Frequency setting pin: connect a frequency-setting resistor to signal GND, or connect an external clock for synchronization. |
| 4 | EN1 | input | Channel 1 and channel 2 SMPS enable pin: apply greater than 0.55 V and less than 6 V to turn on, connect to GND to disable, and attach the adjustable soft-start capacitance here. |
| 5 | PGOOD1 | output | Channel 1 powergood window comparator output; the recommended applied voltage is less than 6 V and the recommended pull-up resistance is 100 kΩ to 1 MΩ. |
| 6 | SKIPSEL1 | input | Skip mode selection: GND selects continuous conduction mode, VREF2 selects Auto Skip, VREG3 selects OOA Auto Skip with maximum 7 skips (suitable for fsw < 400 kHz), and VREG5 selects OOA Auto Skip with maximum 15 skips (suitable for fsw ≥ 400 kHz). |
| 7 | CSP1 | bidirectional | Channel 1 current sense comparator non-inverting input; an RC network with a high-quality X5R or X7R ceramic capacitor extracts the DCR voltage drop, with 0.1 µF given as a good starting value. |
| 8 | CSN1 | input | Channel 1 current sense comparator inverting input; it also serves as the power supply for the current sense circuit at 5 V or higher output voltage settings and as the output discharge terminal. |
| 9 | VFB1 | input | Channel 1 SMPS voltage feedback input; connect the feedback resistor divider, referenced to signal GND. |
| 10 | COMP1 | input | Channel 1 error amplifier output for current mode loop compensation; connect R (and C if required) from this pin to VREF2. |
| 11 | IMON1 | output | Channel 1 current monitor output, with an RC filter recommended; the monitor output is 3.00 V typical at VCSP-VCSN = 60 mV (3.25 V max, 2.75 V min at 25°C). |
| 12 | EN | input | Enable pin for the VREF2 and VREG5 linear regulators: apply greater than 1.2 V and less than 6 V to turn on, and connect to GND to disable. |
| 13 | VREF2 | power_out | 2-V reference output; bypass to signal GND with 0.22 µF of ceramic capacitance. |
| 14 | IMON2 | output | Channel 2 current monitor output, with an RC filter recommended. |
| 15 | COMP2 | input | Channel 2 error amplifier output for current mode loop compensation; connect R (and C if required) from this pin to VREF2. |
| 16 | VFB2 | input | Channel 2 SMPS voltage feedback input; connect the feedback resistor divider, referenced to signal GND. |
| 17 | CSN2 | input | Channel 2 current sense comparator inverting input; it also serves as the power supply for the current sense circuit at 5 V or higher output voltage settings and as the output discharge terminal. |
| 18 | CSP2 | bidirectional | Channel 2 current sense comparator non-inverting input; an RC network with a high-quality X5R or X7R ceramic capacitor extracts the DCR voltage drop, with 0.1 µF given as a good starting value. |
| 19 | SKIPSEL2 | input | Skip mode selection: GND selects continuous conduction mode, VREF2 selects Auto Skip, VREG3 selects OOA Auto Skip with maximum 7 skips (suitable for fsw < 400 kHz), and VREG5 selects OOA Auto Skip with maximum 15 skips (suitable for fsw ≥ 400 kHz). |
| 20 | PGOOD2 | output | Channel 2 powergood window comparator output; the recommended applied voltage is less than 6 V and the recommended pull-up resistance is 100 kΩ to 1 MΩ. |
| 21 | EN2 | input | Channel 1 and channel 2 SMPS enable pin: apply greater than 0.55 V and less than 6 V to turn on, connect to GND to disable, and attach the adjustable soft-start capacitance here. |
| 22 | VREG3 | power_out | Always-alive 3.3 V, 10 mA low dropout linear regulator output; bypass to signal GND with more than 1 µF of ceramic capacitance, running from VIN or from VREG5 when switched over to V5SW. |
| 23 | VIN | power_in | Supply input for the 5 V and 3.3 V linear regulators, typically connected to VBAT; recommended supply voltage range is 4.5 V to 32 V. |
| 24 | DRVH2 | output | High-side MOSFET gate driver output for channel 2, rated source 1.7 Ω and sink 1.0 Ω, SW-node referenced floating driver whose drive voltage is VBST to SW. |
| 25 | SW2 | bidirectional | High-side MOSFET gate driver return for channel 2 (switch node reference for DRVH2 and VBST2). |
| 26 | VBST2 | input | Boot strap supply input for the channel 2 high-side N-channel driver; connect a capacitor of 0.1 µF or greater from this pin to SW2, with an optional Schottky diode from VREG5 to this pin. |
| 27 | DRVL2 | output | Channel 2 low-side MOSFET gate driver output, rated source 1.3 Ω and sink 0.7 Ω, GND referenced. |
| 28 | GND | power_in | Ground. |
| 29 | VREG5 | power_out | 5 V, 100 mA low dropout linear regulator output, bypassed to power GND with a 10 µF ceramic capacitor; runs from VIN, shuts off with EN, and switches over to V5SW when 4.8 V or above is provided. |
| 30 | DRVL1 | output | Channel 1 low-side MOSFET gate driver output, rated source 1.3 Ω and sink 0.7 Ω, GND referenced. |
| 31 | VBST1 | input | Boot strap supply input for the channel 1 high-side N-channel driver; connect a capacitor of 0.1 µF or greater from this pin to SW1, with an optional Schottky diode from VREG5 to this pin. |
| 32 | SW1 | bidirectional | High-side MOSFET gate driver return for channel 1 (switch node reference for DRVH1 and VBST1). |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN shutdown current | I(VINSDN) |  | 7 | 15 | µA | TA = 25°C, No Load, EN = 0V, V5SW = 0 V | 4 |
| VIN standby current | I(VINSTBY) |  | 80 | 120 | µA | TA = 25°C, No Load, EN1 = EN2 = V5SW = 0 V | 4 |
| VREF2 output voltage | V(VREF2) | 1.98 | 2 | 2.02 | V | I(VREF2) < ±10 µA, TA = 25°C | 4 |
| VREG3 output voltage | V(VREG3) | 3.279 | 3.313 | 3.347 | V | V5SW = 0 V, I(VREG3) = 0 mA, TA = 25°C | 4 |
| VREG3 output voltage | V(VREG3) | 3.135 | 3.3 | 3.4 | V | V5SW = 0 V, 0 mA < I(VREG3) < 10 mA, 5.5 V < VIN < 32 V | 4 |
| VREG3 output current | I(VREG3) | 10 | 15 | 20 | mA | VREG3 = 3 V | 4 |
| VREG5 output voltage | V(VREG5) | 4.99 | 5.04 | 5.09 | V | V5SW = 0 V, I(VREG5) = 0 mA, TA = 25°C | 4 |
| VREG5 output voltage | V(VREG5) | 4.9 | 5.03 | 5.15 | V | V5SW = 0 V, 0 mA < I(VREG5) < 100 mA, 6 V < VIN < 32 V | 4 |
| VREG5 output voltage | V(VREG5) | 4.5 | 5.03 | 5.15 | V | V5SW = 0 V, 0 mA < I(VREG5) < 100 mA, 5.5 V < VIN < 32 V | 4 |
| VREG5 output current | I(VREG5) | 100 | 150 | 200 | mA | V5SW = 0 V, VREG5 = 4.5 V | 4 |
| VREG5 output current (V5SW supplied) | I(VREG5) | 200 | 300 | 400 | mA | V5SW = 5 V, VREG5 = 4.5 V | 4 |
| Switchover threshold | V(THV5SW) | 4.55 | 4.7 | 4.8 | V | Turning on | 4 |
| VFB regulation voltage | V(VFB) | 0.9925 | 1 | 1.0075 | V | TA = 25°C, No Load | 4 |
| VFB regulation voltage over temperature | V(VFB) | 0.99 | 1 | 1.01 | V | TA = –40°C to 85°C, No Load | 4 |
| VFB input current | I(VFB) | -50 |  | 50 | nA | VFBx = 1.05 V, COMPx = 1.8 V, TA = 25°C | 4 |
| COMP clamp voltage | VCOMP | 2.18 | 2.22 | 2.26 | V |  | 4 |
| COMP negative clamp voltage | VCOMPN | 1.73 | 1.77 | 1.81 | V |  | 4 |
| PG threshold, PG in from lower | V(THPG) | 92.5 | 95 | 97.5 | % | PG in from lower | 5 |
| PG threshold, PG in from higher | V(THPG) | 102.5 | 105 | 107.5 | % | PG in from higher | 5 |
| PGOOD delay | t(PGDLY) | 0.8 | 1 | 1.2 | ms | Delay for PG in | 5 |
| Switching frequency | f(SW) | 273 | 303 | 333 | kHz | Rf = 330 kΩ | 5 |
| RF threshold | V(THRF) | 0.7 | 1.3 | 2 | V | Lo to Hi | 5 |
| DRVH-off to DRVL-on dead time | tD | 10 | 30 | 50 | ns | DRVH-off to DRVL-on | 5 |
| Current limit threshold | V(OCL) | 55 | 60 | 68 | mV | 2 V < VCSNx < 12.6 V, TA = –40 to 85°C | 5 |
| Current limit threshold | V(OCL) | 54 | 60 | 72 | mV | 0.95 V < VCSNx < 12.6 V, TA = –40 to 85°C | 5 |
| Negative current limit threshold | V(OCLN-LV) | -77 | -60 | -49 | mV | 0.95 V < VCSNx < 12.6 V, TA = –40 to 85°C | 5 |
| EN1/EN2 threshold | V(EN12) | 0.45 | 0.5 | 0.55 | V | Wake up | 6 |
| Current monitor output voltage | V(IMON) | 2.75 | 3 | 3.25 | V | VCSPx–VCSNx = 60 mV, 0.95 V < VCSNx < 12.6 V, TA = 25°C | 6 |
| OVP trip threshold | V(OVP) | 110 | 115 | 120 | % | OVP detect | 6 |
| UVP trip threshold | V(UVP) | 65 | 70 | 73 | % | UVP detect | 6 |
| VREG5 UVLO threshold | V(UVREG5) | 4.1 | 4.2 | 4.3 | V | Wake up | 6 |
| VREG3 UVLO threshold | V(UVREG3) | 3 | 3.1 | 3.2 | V | Wake up | 6 |
| EN threshold | V(EN) | 0.8 | 1 | 1.2 | V | Wake up | 6 |
| Input voltage range | VIN | -0.3 |  | 34 | V |  | 3 |
| Boot voltage range | VBST1, VBST2 | -0.3 |  | 39 | V |  | 3 |
| Boot voltage range wrt SW | VBST1, VBST2 | -0.3 |  | 7 | V | Voltage with respect to the corresponding SW terminal | 3 |
| Switch node voltage range | SW1, SW2 | -5 |  | 34 | V |  | 3 |
| Current sense input voltage range | CSN1, CSN2, CSP1, CSP2 | -1 |  | 13.5 | V |  | 3 |
| Logic input voltage range | EN, EN1, EN2, SKIPSEL1, SKIPSEL2, VFB1, VFB2 | -0.3 |  | 7 | V |  | 3 |
| V5SW voltage range | V5SW | -1 |  | 7 | V |  | 3 |
| V5SW voltage range to VREG5 | V5SW (to VREG5) | -7 |  | 7 | V | When EN is high and V5SW is grounded, or voltage is applied to V5SW when EN is low | 3 |
| High-side gate driver voltage range | DRVH1, DRVH2 | -5 |  | 39 | V |  | 3 |
| High-side gate driver voltage range wrt SW | DRVH1, DRVH2 | -0.3 |  | 7 | V | Voltage with respect to the corresponding SW terminal | 3 |
| Output and logic I/O voltage range | COMP1, COMP2, DRVL1, DRVL2, IMON1, IMON2, PGOOD1, PGOOD2, RF, VREF2, VREG5 | -0.3 |  | 7 | V |  | 3 |
| VREG3 voltage range | VREG3 | -0.3 |  | 3.6 | V |  | 3 |
| Junction temperature | TJ |  |  | 150 | °C |  | 3 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 3 |
| Input voltage supply | VIN | 4.5 |  | 32 | V |  | 3 |
| V5SW voltage | V5SW | -0.8 |  | 6 | V |  | 3 |
| Boot voltage | VBST1, VBST2 | -0.1 |  | 37 | V |  | 3 |
| High-side gate driver voltage | DRVH1, DRVH2 | -4 |  | 37 | V |  | 3 |
| High-side gate driver voltage wrt SW | DRVH1, DRVH2 (wrt SW1, 2) | -0.1 |  | 6 | V |  | 3 |
| Switch node voltage | SW1, SW2 | -4 |  | 32 | V |  | 3 |
| Current sense input voltage | CSP1, CSP2, CSN1, CSN2 | -0.8 |  | 13 | V |  | 3 |
| Logic and I/O voltage | COMP1, COMP2, DRVL1, DRVL2, EN, EN1, EN2, IMON1, IMON2, PGOOD1, PGOOD2, RF, SKIPSEL1, SKIPSEL2, VFB1, VFB2, VREF2, VREG5 | -0.1 |  | 6 | V |  | 3 |
| VREG3 voltage | VREG3 | -0.1 |  | 3.5 | V |  | 3 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 3 |
| Power rating, 32-pin RTV | PD |  |  | 1.7 | W | TA < 25°C | 3 |
| Power rating, 32-pin RTV at TA = 85°C | PD |  |  | 0.7 | W | TA = 85°C | 3 |
| Derating factor, 32-pin RTV |  |  | 17 |  | mW/°C | Above TA = 25°C | 3 |

## CAD (KiCad official)

- Symbol: `TPS51222RTVR`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `tps51222rtvr-etched.step` / `tps51222rtvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps51222rtvr.step` / `tps51222rtvr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps51222) (45 pp, sha256 `287579365d9552a4`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps51222rtvr-datasheet.pdf)