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TPS40425RHAR

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Texas Instruments DC-DC Converters, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS40425RHAR

Texas Instruments · DC-DC Converters · VQFN-40-EP(6x6)

TPS40425RHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC bidirectional External clock synchronization pin; for 1-, 2- or 4-phase operation the sync frequency must be 4x the switching frequency, for 3-phase it must be 3x, as a 50% duty square wave with high threshold above 2 V and low threshold below 0.8 V.
2 PHSET bidirectional Phase-set pin for multiphase operation, connected between controllers in 3- and 4-phase configurations to set the phase relationship; leave floating for dual-output or two-phase operation.
3 CNTL1 input Logic-level input that starts or stops channel 1; when left floating an internal 6 µA current source pulls it up to BP5.
4 CNTL2 input Logic-level input that starts or stops channel 2; when left floating an internal 6 µA current source pulls it up to BP5.
5 SMBALERT output PMBus alert output used to signal faults or warnings to the bus master via the SMBus alert response protocol.
6 PMBDATA bidirectional PMBus data pin, requires an external pull-up when used; the datasheet specifies 400 kHz PMBus operation with VOL max 0.4 V at 4 mA sink.
7 PMBCLK input PMBus clock input supporting 100 kHz and 400 kHz bus speeds.
8 AGND power_in Analog ground for analog signals; connect directly to the thermal pad, which is the only connection between AGND and PGND.
9 AVSDATA input AVS data line for the high-speed AVSBus interface, 1.8 V or 2.5 V logic levels; may be left floating or tied to GND if AVS is disabled.
10 AVSCLK input AVS clock input for the high-speed AVSBus interface, 10 MHz to 30 MHz, 1.8 V or 2.5 V logic levels; may be left floating or tied to GND if AVS is disabled.
11 ADDR1 input High-order PMBus address pin; connect a resistor to AGND per the E96 value table (sets address digit 0-7).
12 ADDR0 input Low-order PMBus address pin; connect a resistor to AGND per the E96 value table (sets address digit 0-7).
13 GSNS2 input Negative voltage-sense input for channel 2 output voltage; connect to ground for slave-channel or single-channel use as specified in the pin configuration tables.
14 VSNS2 input Positive voltage-sense input for channel 2 output voltage; may be tied to ground or to the output voltage in multiphase use as stated in the pin configuration tables.
15 COMP2 output Output of error amplifier 2 and connection node for the loop feedback compensation network.
16 FB2 input Inverting input of error amplifier 2 that equals the internal reference (600 mV) in normal operation; connect to BP5 to configure the channel as a slave.
17 FLT2 bidirectional Channel 2 fault signal, pulled up to BP3 through an internal 100 kΩ resistor; an external pull-down on this pin shuts channel 2 off.
18 CS2N input Negative input of the channel 2 current-sense amplifier; internally pulled up to 1.24 V through 4 kΩ during smart power stage operation.
19 CS2P input Positive input of the channel 2 current-sense amplifier; differential CSxP-CSxN limited to 60 mV in non-smart power mode.
20 TSNS2 input External temperature-sense input for channel 2 (ΔVbe of external transistor or smart power stage TAO signal); absolute maximum 3.6 V.
21 ISH2 input Current-share signal for channel 2 in multiphase operation; connect to the ISH bus.
22 PG2 output Open-drain power-good output for channel 2, internally pulled to ground when the output is outside its PGOOD window; absolute maximum 7 V.
23 PWM2 output PWM drive signal for channel 2 with three levels (high, low and tri-state); absolute maximum 7 V.
24 VDD power_in Controller supply input, recommended 4.5 V to 20 V (absolute maximum 22 V); place at least a 1 µF low-ESR ceramic capacitor to AGND close to the pin.
25 BP5 power_out Internal regulator output (about 5 V) for bypass; place at least 1 µF low-ESR ceramic capacitor to PGND close to the pin, maximum recommended 10 µF.
26 BP3 power_out 3.3 V bias output for logic; place at least 0.33 µF low-ESR ceramic capacitor to AGND close to the pin, maximum recommended 10 µF.
27 PGND power_in Power ground for the BP5 bypass capacitor; connect directly to the thermal pad.
28 PWM1 output PWM drive signal for channel 1 with three levels (high, low and tri-state); absolute maximum 7 V.
29 PG1 output Open-drain power-good output for channel 1, internally pulled to ground when the output is outside its PGOOD window; absolute maximum 7 V.
30 ISH1 input Current-share signal for channel 1 in multiphase operation; connect to the ISH bus.
31 TSNS1 input External temperature-sense input for channel 1 (ΔVbe of external transistor or smart power stage TAO signal); absolute maximum 3.6 V.
32 CS1P input Positive input of the channel 1 current-sense amplifier; differential CSxP-CSxN limited to 60 mV in non-smart power mode.
33 CS1N input Negative input of the channel 1 current-sense amplifier; internally pulled up to 1.24 V through 4 kΩ during smart power stage operation.
34 FLT1 bidirectional Channel 1 fault signal, pulled up to BP3 through an internal 100 kΩ resistor; an external pull-down on this pin shuts channel 1 off.
35 FB1 input Inverting input of error amplifier 1 that equals the internal reference (600 mV) in normal operation; connect to BP5 to configure the channel as a slave.
36 COMP1 output Output of error amplifier 1 and connection node for the loop feedback compensation network.
37 VSNS1 input Positive voltage-sense input for channel 1 output voltage, used with GSNS1 as a differential remote-sense pair.
38 GSNS1 input Negative voltage-sense input for channel 1 output voltage, used with VSNS1 as a differential remote-sense pair.
39 DIFFO1 output Channel 1 remote-sense amplifier output; maximum output voltage 4.7 V, and the output must stay below BP5 minus 0.2 V.
40 RT input Oscillator frequency-setting pin; connect a resistor to AGND to set fSW from 200 kHz to 1.5 MHz.
41 PAD power_in Exposed thermal pad on the underside of the package; solder to the power-ground plane with sufficient vias, and it is the connection point for the AGND and PGND pins.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Power Management (PMIC)
Pins 41

CAD (KiCad official)

  • Symbol: TPS40425RHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: tps40425rhar-etched.step / tps40425rhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps40425rhar.step / tps40425rhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (93 pp, sha256 5b2a7a765da52948, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF