# TPS40200DRBT

**Texas Instruments** · DC-DC Converters · HVSON-8-EP(3x3)

TPS40200DRBT from Texas Instruments, in a HVSON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RC | input | Switching frequency setting RC network: connect a capacitor from RC to GND and a resistor from VDD to RC, and the pin may be synchronized by an external open-drain clock pulled to GND; absolute maximum range is -0.3 V to 5.5 V. |
| 2 | SS | input | Soft-start programming pin: a capacitor from SS to GND sets the soft-start time, pulling it below 150 mV stops output switching (shutdown), and it also serves as the overcurrent restart timer; absolute maximum range is -0.3 V to 9.0 V. |
| 3 | COMP | output | Error amplifier output: connect the control-loop compensation network from COMP to FB; absolute maximum range is -0.3 V to 9.0 V. |
| 4 | FB | input | Error amplifier inverting input: connect the feedback resistor network center tap to this pin; absolute maximum range is -0.3 V to 5.5 V. |
| 5 | GND | power_in | Device ground. |
| 6 | GDRV | output | Driver output for an external P-channel MOSFET, with the absolute maximum range stated as VIN - 10 V to VIN. |
| 7 | ISNS | input | Current-sense comparator input: connect a current sense resistor between ISNS and VDD to set the desired overcurrent threshold; absolute maximum range is -0.3 V to 52 V. |
| 8 | VDD | power_in | System input voltage (4.5 V to 52 V recommended operating range): connect a local bypass capacitor from VDD to GND. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVSON-8-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 9 |

## CAD (KiCad official)

- Symbol: `TPS40200DRBT`
- Footprint: `Package_SON:HVSON-8-1EP_3x3mm_P0.65mm_EP1.6x2.4mm`
- 3D model: HVSON-8-EP(3x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps40200drbt-etched.step` / `tps40200drbt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps40200drbt.step` / `tps40200drbt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps40200) (52 pp, sha256 `a3e23ec7367038ec`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps40200drbt-datasheet.pdf)