TPS3703A7080DSERQ1

Texas Instruments · Supervisor And Reset ICs · WSON-6(1.5x1.5)

TPS3703A7080DSERQ1 from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SENSE	input	Input for the monitored supply voltage rail; RESET is driven low when SENSE rises above VIT+(OV) or falls below VIT-(UV), with VSENSE rated 0 V to 5.5 V, and SENSE should be tied to VDD to monitor the VDD supply.
2	VDD	power_in	Supply voltage input rated 1.7 V to 5.5 V (absolute maximum 6 V), with a 0.1-µF ceramic capacitor recommended close to this pin.
3	CT	input	Capacitor time-delay pin that selects a fixed reset delay when left floating (CT open) or tied to VDD through a pull-up resistor (10 kΩ recommended), and programs the delay when an external capacitor is connected to ground; CT voltage is limited to VDD or 5.5 V, whichever is smaller.
4	RESET	output	Active-low open-drain output that goes low when SENSE is outside the overvoltage or undervoltage thresholds or during UVLO and manual reset; it requires a pull-up resistor, with output voltage up to 5.5 V and output current from 0.3 mA to 10 mA (absolute maximum ±40 mA).
5	GND	power_in	Ground reference pin for the device.
6	MR	input	Manual reset input that asserts RESET when pulled to a logic low (VMR_L), with the reset released after the reset delay time tD expires once MR returns high; MR is internally pulled up to VDD so it may be left floating, and its voltage is rated 0 V to 5.5 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WSON-6(1.5x1.5)
Category	Power Management (PMIC)
Pins	6

CAD (KiCad official)

Symbol: TPS3703A7080DSERQ1
Footprint: Package_SON:WSON-6_1.5x1.5mm_P0.5mm
3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
3D model files: tps3703a7080dserq1-etched.step / tps3703a7080dserq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3703a7080dserq1.step / tps3703a7080dserq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (40 pp, sha256 05a6581745cb5982, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TPS3703A7080DSERQ1

**Texas Instruments** · Supervisor And Reset ICs · WSON-6(1.5x1.5)

TPS3703A7080DSERQ1 from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SENSE | input | Input for the monitored supply voltage rail; RESET is driven low when SENSE rises above VIT+(OV) or falls below VIT-(UV), with VSENSE rated 0 V to 5.5 V, and SENSE should be tied to VDD to monitor the VDD supply. |
| 2 | VDD | power_in | Supply voltage input rated 1.7 V to 5.5 V (absolute maximum 6 V), with a 0.1-µF ceramic capacitor recommended close to this pin. |
| 3 | CT | input | Capacitor time-delay pin that selects a fixed reset delay when left floating (CT open) or tied to VDD through a pull-up resistor (10 kΩ recommended), and programs the delay when an external capacitor is connected to ground; CT voltage is limited to VDD or 5.5 V, whichever is smaller. |
| 4 | RESET | output | Active-low open-drain output that goes low when SENSE is outside the overvoltage or undervoltage thresholds or during UVLO and manual reset; it requires a pull-up resistor, with output voltage up to 5.5 V and output current from 0.3 mA to 10 mA (absolute maximum ±40 mA). |
| 5 | GND | power_in | Ground reference pin for the device. |
| 6 | MR | input | Manual reset input that asserts RESET when pulled to a logic low (VMR_L), with the reset released after the reset delay time tD expires once MR returns high; MR is internally pulled up to VDD so it may be left floating, and its voltage is rated 0 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6(1.5x1.5) |
| Category | Power Management (PMIC) |
| Pins | 6 |

## CAD (KiCad official)

- Symbol: `TPS3703A7080DSERQ1`
- Footprint: `Package_SON:WSON-6_1.5x1.5mm_P0.5mm`
- 3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
- 3D model files: `tps3703a7080dserq1-etched.step` / `tps3703a7080dserq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps3703a7080dserq1.step` / `tps3703a7080dserq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps3703-q1) (40 pp, sha256 `05a6581745cb5982`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps3703a7080dserq1-datasheet.pdf)